Process of forming high-k gate dielectric layer for metal oxide semiconductor transistor
View Patent ↗A process of forming a high-k gate dielectric layer is applied in forming semiconductor devices such as metal oxide semiconductor transistor or memory devices. A metal layer such as Hf or Zr is formed on a substrate. The substrate is then dipped in an acidic solution such as a nitric acid aqueous solution to form a high-K metal oxide layer including oxides or silicate with a predetermined thickness. Thereby, leakage current is effectively reduced to meet the requirement of currently technology nodes.
1. A process of forming a high-K gate dielectric layer in a metal oxide semiconductor transistor, the process comprising:
a). providing a substrate, the step of providing the substrate including:
a1). removing a native oxide layer that has been formed on the substrate;
a2). forming an oxide layer on the substrate; and
a3). forming a nitride layer on the oxide layer;
b). forming a metal layer on the nitride layer;
c). dipping the substrate in an acidic solution to form a high-k metal oxide layer;
e). applying a conductive material over the high-k metal oxide layer;
f). etching the conductive layer to expose a source anticipating region and a drain anticipating region; and
g). doping ions to form a drain and a source.
2. The process of claim 1 , wherein the material of the substrate is one selected from the group consisting of Si, strained Si, SiGe, Ge, IIIB-group elements, IVB-group elements and VB-group elements.
3. The process of claim 1 , wherein the material of metal layer is one selected from the group consisting of Hf, Zr, La and Y.
4. The process of claim 1 , wherein the material of the high-k metal oxide layer is one selected from the group consisting of HfO2, ZrO2, La2O3, Y2O3, HfSiO and ZrSiO.
5. The process of claim 1 , wherein the metal layer has a thickness of about 3 angstroms and 60 angstroms.
6. The process of claim 5 , wherein the acidic solution is a nitric acid aqueous solution of a concentration of more than 0.1%.
7. The process of claim 1 , wherein the step b) is performed by one of CVD, PVD, MBE, anode plating and electroless plating to form the metal layer.
8. The process of claim 1 , wherein the conductive layer is formed of metals or polysilicon.
9. The process of claim 1 , wherein the process is applied to form a memory device.
10. The process of claim 1 , wherein after the step c), a high-temperature annealing is performed to remove impurities in the high-K metal oxide layer.
11. The process of claim 1 , wherein the step a2) includes forming the oxide layer to contact a top surface of the substrate.
12. The process of claim 11 , wherein the step a3) includes forming the nitride layer to contact a top surface of the oxide layer.
13. The process of claim 1 , wherein the step a3) includes forming the nitride layer to contact a top surface of the oxide layer.