Patent Assignment
Reel/Frame 015639/0923
Assignment of Assignor's Interest
Recorded: 2004-08-02
Pages: 3
Assignors
MATSUSHITA, HIROSHI
Executed: 2004-07-27
KADOTA, KENICHI
Executed: 2004-07-27
KAWABATA, KENJI
Executed: 2004-07-27
SHIOYAMA, YOSHIYUKI
Executed: 2004-07-27
Assignee
KABUSHIKI KAISHA TOSHIBA
1-1, SHIBAURA 1-CHOME, MINATO-KU, TOKYO, JAPAN
Covered Property
(1)
Method for Analyzing Fail Bit Maps of Wafers and Apparatus Therefor