Patent Assignment
Reel/Frame 016596/0260
Assignment of Assignor's Interest
Recorded: 2005-05-24
Pages: 3
Assignors
KINOSHITA, KOICHI
Executed: 2005-04-05
ITAKA, YASUHITO
Executed: 2005-04-05
SUGAHARA, TAKESHI
Executed: 2005-04-05
Assignee
KABUSHIKI KAISHA TOSHIBA
1-1, SHIBAURA 1-CHOME, MINATO-KU, TOKYO 105-8001, JAPAN
Covered Property
(1)
Semiconductor Integrated Circuit Device Formed by Automatic Layout Wiring by Use of Standard Cells and Design Method of Fixing Its Well Potential