Patent Assignment
Reel/Frame 016770/0250
Assignment of Assignor's Interest
Recorded: 2005-07-08
Pages: 3
Assignor
PARRIS, MICHAEL C.
Executed: 2005-07-05
Assignees
UNITED MEMORIES, INC.
4815 LIST DRIVE, SUITE 109, COLORADO SPRINGS, COLORADO, 80919
SONY CORPORATION
6-7-35 KITA-SHINAGAWA SHINAGAWA-KU, TOKYO 141-0001, JAPAN
Covered Property
(1)
Layout Area Efficient, High Speed, Dynamic Multi-Input Exclusive or (Xor) and Exclusive nor (Xnor) Logic Gate Circuit Designs for Integrated Circuit Devices
Related Assignments
(5)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 6, 2010
From: SONY CORPORATION
To: UNITED MEMORIES, INC.
Reel/Frame 024185/0758 →
Assignment of Assignor's Interest
Dec 1, 2010
From: UNITED MEMORIES, INC.
To: TESSERA INTELLECTUAL PROPERTIES, INC.
Reel/Frame 025596/0520 →
Change of Name
Jun 8, 2011
From: TESSERA INTELLECTUAL PROPERTIES, INC.
To: INVENSAS CORPORATION
Reel/Frame 026423/0286 →
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Release of Security Interest
Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →