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System and Method for Managing Security Key Architecture in Multiple Security Contexts of a Network Environment

Static Random Access Memory (Sram) Compatible, High Availability Memory Array and Method Employing Synchronous Dynamic Random Access Memory (Dram) in Conjunction with a Data Cache and Separate Read and Write Registers and Tag Blocks

Data Inversion Register Technique for Integrated Circuit Memory Testing

Short-Circuit Charge-Sharing Technique for Integrated Circuit Devices

Multiple Bus Charge Sharing

Optimized Charge Sharing for Data Bus Skew Applications

Switched Capacitor Charge Sharing Technique for Integrated Circuit Devices Enabling Signal Generation of Disparate Selected Signal Values

Layout Area Efficient, High Speed, Dynamic Multi-Input Exclusive or (Xor) and Exclusive nor (Xnor) Logic Gate Circuit Designs for Integrated Circuit Devices

Static Random Access Memory (Sram) Compatible, High Availability Memory Array and Method Employing Synchronous Dynamic Random Access Memory (Dram) in Conjunction with a Data Cache and Separate Read and Write Registers and Tag Blocks

Simultaneous Function Dynamic Random Access Memory Device Technique

Test Interface for Verification of High Speed Embedded Synchronous Dynamic Random Access Memory (Sdram) Circuitry