Data inversion register technique for integrated circuit memory testing
View Patent ↗A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.
1. A testing technique for an integrated circuit device including a memory array, said technique comprising:
determining a pattern of data inputs to be applied to said memory array;
inverting selected ones of said pattern of data inputs;
applying said pattern of data inputs including said inverted selected ones to said memory array;
reading out a contents of said memory array;
further inverting said previously inverted selected ones of said applied pattern from said read out contents; and
comparing said applied pattern of data inputs with said read out contents.
2. The technique of claim 1 wherein said determining of said pattern of data inputs comprises:
selecting a pattern of said data input intended to test an input/output portion of said integrated circuit device.
3. The technique of claim 2 wherein said selecting of said pattern comprises:
utilizing data stripes in said selected pattern.
4. The technique of claim 1 wherein said determining of said pattern of data inputs comprises:
selecting a pattern of said data input intended to test said memory array of said integrated circuit device.
5. The technique of claim 2 wherein said selecting of said pattern comprises:
utilizing column stripes in said selected pattern.
6. The technique of claim 1 wherein a number of said data inputs is less than the width of said memory array data bus.
7. The technique of claim 6 wherein said number of said data inputs is one.
8. A testing technique for an integrated circuit device including a memory array, said technique comprising:
dynamically providing a pattern of data inputs to be applied to said memory array;
inverting selected ones of said pattern of data inputs;
applying said pattern of data inputs including said inverted selected ones to said memory array;
reading out a contents of said memory array;
further inverting said previously inverted selected ones of said applied pattern from said read out contents; and
comparing said applied pattern of data inputs with said read out contents.
9. The technique of claim 8 wherein said dynamically providing said pattern of data inputs comprises:
selecting a pattern of said data input intended to test an input/output portion of said integrated circuit device.
10. The technique of claim 9 wherein said selecting of said pattern comprises:
utilizing data stripes in said selected pattern.
11. The technique of claim 8 wherein said dynamically providing said pattern of data inputs comprises:
selecting a pattern of said data input intended to test said memory array of said integrated circuit device.
12. The technique of claim 9 wherein said selecting of said pattern comprises:
utilizing column stripes in said selected pattern.
13. The technique of claim 8 wherein said dynamically providing said pattern of data inputs is carried out by means of a programmable register.
14. The technique of claim 8 wherein a number of said data inputs is less than the width of said memory array data bus.
15. The technique of claim 14 wherein said number of said data inputs is one.