Short-circuit charge-sharing technique for integrated circuit devices
View Patent ↗A short-circuit charge-sharing technique which allows charge-sharing between two or more circuits with a simple shorting transistor controlled to achieve the desired operating voltage levels. The shorting transistor which can be either a P-channel Metal Oxide Semiconductor (PMOS) or an N-channel Metal Oxide Semiconductor (NMOS) device and can be controlled utilizing the same clock that enables the drive of the signals between which charge-sharing occurs. In operation, the desired operating voltage levels can be regulated by increasing and decreasing the pulse width of the control circuit output to the gate of the shorting transistor.
1. A charge-sharing technique between first and second signal lines comprising:
sensing a voltage level on said first signal line increasing above a first determined voltage level;
coupling said first signal line to said second signal line for a first time period to reduce said sensed voltage level toward said first determined voltage level;
alternatively sensing said voltage level on said first signal line decreasing below said first determined voltage level; and
coupling said first signal line to said second signal line for a second time period shorter than said first time period to allow said sensed voltage level to increase toward said first determined voltage level.
2. The technique of claim 1 wherein said first determined voltage level is a fraction of a supply voltage level.
3. The technique of claim 1 wherein said steps of sensing and alternatively sensing are carried out by:
comparing said first determined voltage level to a supply voltage level.
4. The technique of claim 1 further comprising:
further sensing a voltage level on said second signal line increasing above a second determined voltage level;
further coupling said second signal line to said first signal line for a third time period to reduce said sensed voltage level toward said second determined voltage level;
further alternatively sensing said voltage level on said second signal line decreasing below said first determined voltage level; and
further coupling said second signal line to said first signal line for a fourth time period greater than said third time period to allow said sensed voltage level to increase toward said second determined voltage level.
5. The technique of claim 4 wherein said second determined voltage level is a fraction of a supply voltage level.
6. The technique of claim 4 wherein said steps of further sensing and further alternatively sensing are carried out by:
further comparing said second determined voltage level to a supply voltage level.
7. A circuit for charge-sharing between first and second signal lines comprising:
a control circuit receiving a clock input signal and providing a gating signal output wherein said control circuit includes a first comparator for comparing a voltage level on said first signal line to a determined first voltage level wherein a duration of said gating signal is increased to reduce a sensed voltage level on said first signal line and increase a sensed voltage level on said second signal line; and
a switching device coupled between said first and second signal lines and having a control terminal coupled to receive said gating signal output of said control circuit.
8. A circuit for charge-sharing between first and second signal lines comprising:
a control circuit receiving a clock input signal and providing a gating signal output wherein said control circuit includes a first comparator for comparing a voltage level on said first signal line to a determined first voltage level wherein said gating signal is pulse width modulated and wherein a duration of said gating signal is decreased to increase a sensed voltage on said first signal line and to decrease a sensed voltage level on said second signal line; and
a switching device coupled between said first and second signal lines and having a control terminal coupled to receive said gating signal output of said control circuit.
9. A circuit for charge-sharing between first and second signal lines comprising:
a control circuit receiving a clock input signal and providing a gating signal output wherein said control circuit includes a first comparator for comparing a voltage level on said first signal line to a determined first voltage level;
a switching device coupled between said first and second signal lines and having a control terminal coupled to receive said gating signal output of said control circuit; and
a second comparator for comparing a voltage level on said second signal line to a determined second voltage level.
10. A circuit for charge-sharing between first and second signal lines comprising:
a control circuit receiving a clock input signal and providing a gating signal output wherein said control circuit includes a first comparator for comparing a voltage level on said first signal line to a determined first voltage level;
a switching device coupled between said first and second signal lines and having a control terminal coupled to receive said gating signal output of said control circuit; and
a second comparator for comparing a voltage level on said second signal line to a determined second voltage level wherein said control circuit is operative to decrease a duration of said gating signal when said voltage level on said second signal line rises above said determined second voltage level and increase a duration of said gating signal when said voltage level on said second signal line falls below said determined second voltage level.
11. A circuit for charge-sharing between first and second signal lines comprising:
a control circuit receiving a clock input signal and providing a gating signal output wherein said control circuit includes a first comparator for comparing a voltage level on said first signal line to a determined first voltage level;
a switching device coupled between said first and second signal lines and having a control terminal coupled to receive said gating signal output of said control circuit;
a second comparator for comparing a voltage level on said second signal line to a determined second voltage level;
a first transistor having a relatively small channel width; and
a second transistor having a relatively large channel width;
said first transistor being operative to increase a width of said gating signal and said second transistor being operative to decrease a width of said gating signal.