Patent Assignment
Reel/Frame 073941/0814
Change of Name
Recorded: 2025-11-24
Pages: 7
Assignor
INVENSAS CORPORATION
Executed: 2021-10-01
Assignee
INVENSAS LLC
3025 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(76)
Method and Apparatus for Packaging Circuit Devices
Patent:
7,535,093 →
Application:
10/094,174 →
Predictive Error Correction Code Generation Facilitating High-Speed Byte-Write in a Semiconductor Memory
Wafer-Leveled Chip Packaging Structure and Method Thereof
Method of Forming Electrode for Semiconductor Device
Methods and Apparatus for Rf Shielding in Vertically-Integrated Semiconductor Devices
Semiconductor Device and Method of Manufacturing a Semiconductor Device
Packaged Stacked Semiconductor Device and Method for Manufacturing the Same
Stacked Integrated Circuit Assembly
Wafer-Leveled Chip Packaging Structure and Method Thereof
Integrated Circuit Package Device with Improved Bond Pad Connections, a Lead-Frame and an Electronic Device
Semiconductor Device and Fabricating Method Thereof
Semiconductor Device
Technique for Reducing Parity Bit-Widths for Check Bit and Syndrome Generation for Data Blocks Through the Use of Additional Check Bits to Increase the Number of Minimum Weighted Codes in the Hamming Code H-Matrix
Short-Circuit Charge-Sharing Technique for Integrated Circuit Devices
Wafer Bonding Method of System in Package
Method of Producing Semiconductor Device and Semiconductor Device
Semiconductor Package Device
Packaged Semiconductor Device and Method of Manufacturing the Packaged Semiconductor Device
Infinitely Stackable Interconnect Device and Method
Non-Volatile Memory Embedded in a Conventional Logic Process and Methods for Operating Same
Non-Volatile Memory Embedded in a Conventional Logic Process and Methods for Operating Same
Vertical Electrical Interconnect Formed on Support Prior to Die Mount
Semiconductor Through Silicon Vias of Variable Size and Method of Formation
Producing a Covered Through Substrate via Using a Temporary Cap Layer
Electrically Interconnected Stacked Die Assemblies
Method of Forming Metal Electrode of System in Package
Wafer Level Surface Passivation of Stackable Integrated Circuit Chips
Semiconductor Chip, Method of Fabricating the Same and Stack Package Having the Same
Dielectric Trenches, Nickel/Tantalum Oxide Structures, and Chemical Mechanical Polishing Techniques
Semiconductor Die Mount by Conformal Die Coating
Method of Manufacturing Semiconductor Device with Electrode for External Connection and Semiconductor Device Obtained by Means of Said Method
Method of Making Integrated Circuit Embedded with Non-Volatile Programmable Memory Having Variable Coupling
Through Substrate Vias for Back-Side Interconnections on Very Thin Semiconductor Wafers
3-D Circuits with Integrated Passive Devices
Semiconductor Device and Method for Fabricating the Same
Semiconductor Chip, Method of Fabricating the Same and Semiconductor Chip Stack Package
Method of Forming an Interconnect Structure
Multi-Layered Metal Interconnection
Stacked Integrated Circuit Assembly
Method for Forming a Through Silicon via (Tsv)
Electrical Interconnect for Die Stacked in Zig-Zag Configuration
Selective Die Electrical Insulation By Additive Process
Electronic Component Used for Wiring and Method for Manufacturing the Same
Stacked Die Assembly Having Reduced Stress Electrical Interconnects
Semiconductor Die Array Structure
Method for Manufacturing a Chip-Size Double Side Connection Package
Method of Operating Integrated Circuit Embedded with Non-Volatile Programmable Memory Having Variable Coupling Related Application Data
Wafer Level Surface Passivation of Stackable Integrated Circuit Chips
Substrates with Through Vias with Conductive Features for Connection to Integrated Circuit Elements, and Methods for Forming Through Vias in Substrates
Methods for Forming Through-Substrate Conductor Filled Vias, and Electronic Assemblies Formed Using Such Methods
Circuit and Technique for Reducing Parity Bit-Widths for Check Bit and Syndrome Generation for Data Blocks Through the Use of Additional Check Bits to Increase the Number of Minimum Weighted Codes in the Hamming Code H-Matrix
Electrical Connector Between Die Pad and Z-Interconnect for Stacked Die Assemblies
Structures with Through Vias Passing Through a Substrate Comprising a Planar Insulating Layer Between Semiconductor Layers
Non-Volatile One-Time-Programmable and Multiple-Time Programmable Memory Configuration Circuit
Semiconductor Device and Method for Manufacturing Semiconductor Device
Semiconductor Device Manufacturing Method and Semiconductor Device
Circuit and Technique for Reducing Parity Bit-Widths for Check Bit and Syndrome Generation for Data Blocks Through the Use of Additional Check Bits to Increase the Number of Minimum Weighted Codes in the Hamming Code H-Matrix
Emi Shield
Method of Operating Integrated Circuit Embedded with Non-Volatile Programmable Memory Having Variable Coupling Related Application Data
Methods of Forming 3-D Circuits with Integrated Passive Devices
Non-Volatile One-Time-Programmable and Multiple-Time Programmable Memory Configuration Circuit
Structures with Through Vias Passing Through a Substrate Comprising a Planar Insulating Layer Between Semiconductor Layers
Chip-Size, Double Side Connection Package and Method for Manufacturing the Same
Dielectric Trenches, Nickel/Tantalum Oxide Structures, and Chemical Mechanical Polishing Techniques
Semiconductor Die Mount by Conformal Die Coating
Methods of Forming 3-D Circuits with Integrated Passive Devices
Structures with Through Vias Passing Through a Substrate Comprising a Planar Insulating Layer Between Semiconductor Layers
Substrates with Through Vias with Conductive Features for Connection to Integrated Circuit Elements, and Methods for Forming Through Vias in Substrates
Structures with Through Vias Passing Through a Substrate Comprising a Planar Insulating Layer Between Semiconductor
Selective Die Electrical Insulation by Additive Process
Electrical Connector Between Die Pad and Z-Interconnect for Stacked Die Assemblies
Methods of Forming 3-D Circuits with Integrated Passive Devices
Laminated Interposers and Packages with Embedded Trace Interconnects
Methods of Forming 3-D Circuits with Integrated Passive Devices
Chip-Size, Double Side Connection Package and Method for Manufacturing the Same
Laminated Interposers and Packages with Embedded Trace Interconnects
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Oct 14, 2013
From: SHARP KABUSHIKI KAISHA
To: INVENSAS CORPORATION
Reel/Frame 031401/0219 →
Security Agreement
Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0807 →
Assignment and Assumption of Security Interest in Patents
Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
Assignment and Assumption of Security Interest in Patents
Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
Security Agreement Supplement
Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
Corrective Assignment to Correct the Remove Application 12092129 Previously Recorded on Reel 038017 Frame 0058. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
Patent Release
Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
Release of Security Interest
Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
Release of Security Interest
Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Release of Security Interest
Jan 28, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CITIBANK, N.A.
Reel/Frame 041114/0044 →
Corrective Assignment to Correct the Remove Patents 8108266 and 8062324 and Replace Them with 6108266 and 8060324 Previously Recorded on Reel 037518 Frame 0292. Assignor(S) Hereby Confirms the Assignment and Assumption of Security Interest in Patents.
Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
Corrective Assignment to Correct the Remove Application 12681366 Previously Recorded on Reel 039361 Frame 0212. Assignor(S) Hereby Confirms the Security Agreement Supplement.
May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
Corrective Assignment to Correct the Remove Application 12681366 Previously Recorded on Reel 038017 Frame 0058. Assignor(S) Hereby Confirms the Security Agreement Supplement.
May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
Corrective Assignment to Correct the to Correct the Application No. from 13,883,290 to 13,833,290 Previously Recorded on Reel 041703 Frame 0536. Assignor(S) Hereby Confirms the the Assignment and Assumption of Security Interest in Patents..
Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
Release of Security Interest
Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 042762 Frame 0145. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 038017 Frame 0058. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 039361 Frame 0212. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 042985 Frame 0001. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
Corrective Assignment to Correct the Remove Application 11759915 and Replace It with Application 11759935 Previously Recorded on Reel 037486 Frame 0517. Assignor(S) Hereby Confirms the Assignment and Assumption of Security Interest in Patents.
Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →