Multi-layered metal interconnection
View Patent ↗A multi-layered metal interconnection includes a diffusion barrier directly formed on a conductive layer, an etching stop layer directly formed on the diffusion barrier, at least one dielectric layer formed over the etch stop layer, at least one of a via formed in the at least one dielectric layer and a trench formed in the at least one dielectric layer.
1. A multi-layered metal interconnection comprising:
a diffusion barrier directly formed on a semiconductor substrate having a conductive layer;
an etching stop layer directly formed on an upper surface of the diffusion barrier; and
at least one inter-metal dielectric layer formed on the etching stop layer and having a via hole and a trench therein, wherein the trench is wider than the via hole; and
metal interconnection filled in the via and the trench,
wherein the via hole is extended to the conductive layer by passing through the diffusion barrier and the etching stop layer.
2. The multi-layered metal interconnection of claim 1 , wherein the diffusion barrier includes SiOF.
3. The multi-layered metal interconnection of claim 1 , wherein the diffusion barrier is in direct contact with an isolation layer formed in the semiconductor substrate.
4. The multi-layered metal interconnection of claim 1 , wherein the diffusion barrier is disposed between the etching stop layer and the semiconductor substrate.
5. The multi-layered metal interconnection of claim 1 , wherein the etching stop layer is substantially formed on an entire upper surface of the diffusion barrier.
6. The multi-layered metal interconnection of claim 1 , further comprising a barrier layer formed on a wall of the via hole and a wall of the trench.
7. The multi-layered metal interconnection of claim 6 , wherein the barrier layer is in direct contact with the diffusion barrier, the etching stop layer, the metal interconnection, and said at least one inter-metal dielectric layer.