Method of making integrated circuit embedded with non-volatile programmable memory having variable coupling
View Patent ↗A programmable non-volatile device is made with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.
1. A method of forming a non-volatile programmable memory device situated on a substrate comprising:
forming a floating gate for the non-volatile programmable memory device from a first layer,
wherein said first layer is shared by the non-volatile programmable memory device and at least one other device situated on the substrate and associated with at least one of a logic gate or a volatile memory; and
forming a drain region comprised of a first drain region and at least one separate second drain region, first and second channel regions respectively for coupling the first drain region and the at least one separate second drain region to a same source region, wherein the first and second channel regions are for conducting current between the same source region and respectively the first drain region and the at least one separate second drain region,
such that
(i) an amount of capacitive coupling between said gate and said drain region is determined by an amount that portions of said gate overlap said first drain region and said at least one second drain region, and
(ii) a voltage applied to at least one of said first drain region or said at least one second drain region can be imparted to the gate through the capacitive coupling between said gate and said drain region to program said programmable memory device to a selected one of at least three logic states.
2. The method of claim 1 wherein said first layer is polysilicon.
3. The method of claim 1 wherein said first layer is an insulating layer.
4. The method of claim 3 wherein said gate further includes impurities, which impurities are introduced during a source or drain implant step.
5. The method of claim 1 wherein said device is formed with n-type channel.
6. The method of claim 1 wherein said non-volatile programmable memory device is embedded in a computing circuit and formed entirely by masks used to form at least one other logic device or memory n-channel device in said processing circuit.
7. The method of claim 6 wherein said non-volatile programmable memory device is embedded in a computing circuit and formed entirely by CMOS processing steps used to form the at least other logic device or memory devices in said computing circuit.
8. The method of claim 1 wherein said non-volatile programmable memory device is associated with at least one of a data encryption circuit, a reference trimming circuit, a manufacturing ID or a security ID.
9. The method of claim 1 , wherein said capacitive coupling takes place in a first trench situated in the substrate.
10. The method of claim 9 wherein a set of second trenches in said substrate are used as embedded DRAM.
11. The method of claim 1 further including a step:
forming a second programmable device on the substrate coupled in a paired latch arrangement with the non-volatile programmable memory device, such that a datum and its compliment can be stored in said paired latch.
12. The method of claim 1 wherein said non-volatile programmable memory device can only be programmed once.
13. The method of claim 1 wherein said non-volatile programmable memory device can be erased and re-programmed.
14. The method of claim 1 wherein said non-volatile programmable memory device is used to store an identification code for a wafer.
15. The method of claim 1 further including a step: programming said non-volatile programmable memory device during manufacture of a wafer to store an identification code.
16. The method of claim 15 further including a step: programming a second non-volatile programmable memory device during manufacture of the wafer to store a second identification code.
17. The method of claim 1 wherein said non-volatile programmable memory device has a non-conducting channel at a completion of manufacturing of such device.
18. The method of claim 1 wherein said non-volatile programmable memory device is part of an array.
19. The method of claim 1 , wherein the device is adapted to be read by a bias voltage applied to at least one of said first drain region or said at least one separate second drain region which is adjusted with time to determine a threshold voltage of said floating gate.
20. The method of claim 1 wherein the non-volatile memory device is adapted so that more than one bit of information can be stored in response to a programming voltage.
21. A method of forming a one-time programmable (OTP) memory device incorporated on a silicon substrate with at least one other additional logic device or non-OTP memory device, wherein said OTP memory device has a drain region capacitively coupled to a floating gate, the method comprising:
forming any and all regions and structures of said OTP memory device in common with corresponding regions and structures used as components of the at least one additional logic device or non-OTP memory device, such that;
(i) an amount of capacitive coupling between said floating gate and each of a first drain region and at least one separate second drain region of said drain region, first and second channel regions respectively for coupling the first drain region and the at least one separate second drain region to a same source region, wherein the first and second channel regions are for conducting current between the same source region and respectively the first drain region and the at least one separate second drain region, is determined by an amount of overlap between said drain region and said floating gate, and
(ii) a voltage applied to at least one of said first drain region or said at least one second drain region can be imparted to the floating gate through the capacitive coupling between said floating gate and said drain region to effect a selected one of a program operation, an erase operation and a read operation.