IP Library Granted Patent US 7,880,292
Granted Patent B2
US 7,880,292 · App. 11/831,515 · Granted Feb 1, 2011

Semiconductor device and fabricating method thereof

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Quick Facts
Patent No.
US 7,880,292
App. No.
11/831,515
Granted
Feb 1, 2011
Kind
B2
Abstract

A semiconductor device that allows an image sensor (in an upper area of a SiP semiconductor device) to exchange signals with a device in a lower area of a SiP semiconductor device. A semiconductor device includes at least one of: A semiconductor substrate having a photodiode area and a transistor area. A PMD (Pre Metal Dielectric) layer formed on and/or over the semiconductor substrate. At least one metal layers formed on and/or over the PMD layer. A first penetrating electrode penetrating the PMD layer and the at least one metal layers. A second penetrating electrode penetrating the semiconductor substrate and connected to the first penetrating electrode.

Claims (45)

1. An apparatus comprising:

a semiconductor substrate;

at least one layer formed over the semiconductor substrate;

a first penetrating electrode formed through said at least one layer; and

a second penetrating electrode formed through the semiconductor substrate, wherein the first penetrating electrode contacts the second penetrating electrode,

wherein said at least one layer comprises at least one dielectric layer.

2. The apparatus of claim 1 , wherein said at least one dielectric layer is a pre metal dielectric layer.

3. The apparatus of claim 1 , wherein said at least one layer comprises at least one metal wiring layer.

4. The apparatus of claim 1 , wherein the semiconductor substrate comprises at least one of a photodiode area and a transistor area.

5. The apparatus of claim 1 , wherein at least one of the first penetrating electrode and the second penetrating electrode comprises at least one of W, Cu, Al, Ag, and Au.

6. The apparatus of claim 1 , comprising a color filter formed over said at least one layer, wherein the color filter is configured to transmit select wavelengths of light.

7. The apparatus of claim 6 , comprising a micro lens formed over the color filter.

8. The apparatus of claim 1 comprising:

a first device formed on a first side of the semiconductor substrate; and

a second device arranged over a second side of the semiconductor substrate, wherein the first device and the second device are electrically coupled by the first penetrating electrode and the second penetrating electrode.

9. The apparatus of claim 8 , wherein the first device is an image sensor.

10. The apparatus of claim 8 , wherein the second device is at least one of:

a central processing unit;

static random access memory;

dynamic random access memory;

flash memory;

logic large scale integration;

a power integrated circuit;

a control integrated circuit;

an analog LSI;

monolithic microwave integrated circuit;

a complementary metal oxide semiconductor radio frequency integrated circuit;

a sensor chip; and

a micro electro mechanical system chip.

11. A method comprising:

forming at least one layer over a semiconductor substrate;

forming a first penetrating electrode through said at least one layer; and

forming a second penetrating electrode through the semiconductor substrate, wherein the first penetrating electrode contacts the second penetrating electrode,

wherein said forming at least one layer comprises forming at least one dielectric layer.

12. The method of claim 11 , wherein said forming at least one layer comprises forming at least one metal wiring layer.

13. The method of claim 11 , comprising forming at least one of a photodiode area and a transistor area in the semiconductor substrate.

14. The method of claim 11 , wherein at least one of the first penetrating electrode and the second penetrating electrode comprises at least one of W, Cu, Al, Ag, and Au.

15. The method of claim 11 , comprising forming a second device on an opposite side of the semiconductor substrate as said at least one layer.

16. The method of claim 11 , wherein the second penetrating electrode is formed after flipping the semiconductor substrate over.

17. The method of claim 11 , wherein said forming the second penetrating electrode comprises grinding a bottom side of the semiconductor substrate to reduce the thickness of the semiconductor substrate.

18. The method of claim 11 , wherein at least one of forming the first penetrating electrode and forming the second penetrating electrode comprises at least one of:

chemical vapor deposition;

physical vapor deposition;

an evaporation process; and

electro chemical plating.

Assignments (8)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073941/0814 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0745 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2014
From: STRATEGIC GLOBAL ADVISORS OF OREGON, INC.
To: INVENSAS CORPORATION
Reel/Frame 033070/0780 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2014
From: DONGBU HIKTEK CO., LTD.
To: STRATEGIC GLOBAL ADVISORS OF OREGON, INC.
Reel/Frame 033010/0184 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2007
From: HAN, JAE-WON
To: DONGBU HITEK CO., LTD.
Reel/Frame 019626/0574 →