Semiconductor device and method of manufacturing a semiconductor device
View Patent ↗A semiconductor device may include the following. A diffusion barrier formed over a semiconductor substrate having a conductive layer. An etching stop layer formed over a diffusion barrier. Inter-metal dielectric (IMD) layers (e.g. having via holes formed over an etching stop layer and trenches wider than the via holes). Metal interconnections that fill via holes and trenches. Via holes in IMD layers may pass through a diffusion barrier and an etching stop layer to connect to a conductive layer in a semiconductor substrate.
1. A method comprising:
forming a diffusion barrier directly on a conductive layer; and
forming an etching stop layer directly on the diffusion barrier, wherein the etching stop layer comprises SiOF; and
forming at least one dielectric layer over the etching stop layer, wherein the at least one dielectric layer comprise a first silane layer formed directly on the etching stop layer, a FSG layer formed directly on the first silane layer and a second silane layer formed directly on the FSG layer; and
forming a via hole and a trench in the at least one dielectric layer to expose the etching stop layer;
cleaning the walls of the via hole and the trench; and then
removing the exposed portions of the etching stop layer and the diffusion barrier to expose the conductive layer.
2. The method of claim 1 , wherein the diffusion barrier comprises SiN.
3. The method of claim 1 , wherein the conductive layer is formed in a semiconductor substrate.
4. The method of claim 1 , wherein the conductive layer is formed in a dielectric layer.
5. The method of claim 1 , wherein the etching stop layer is an etching stop point during formation of the via hole.
6. A method comprising:
forming a diffusion barrier directly on a semiconductor substrate; and then
forming an etching stop layer directly on the diffusion barrier, wherein the etching stop layer comprises a low dielectric material comprising SiOF; and then
forming a plurality of IMD layers over the semiconductor substrate including the etching stop layer, wherein the IMD layers comprise a first silane layer formed over the etching stop layer, a FSG layer formed over the first silane layer and a second silane layer formed over the FSG layer; and then
forming a via hole in the plurality of IMD layers to expose the etching stop layer; and then
forming a trench pattern over the IMD layers; and then
forming a trench by etching the IMD layers using the trench pattern as a mask; and then
removing the trench pattern; and then
removing exposed portions of the etching stop layer and the diffusion barrier layer in the via hole to expose the conductive layer.
7. The method of claim 6 , wherein forming the via holes comprises:
forming a photoresist layer having via hole patterns over the IMD layers; and then
etching the IMD layers using the photoresist layer as a mask.
8. The method of claim 6 , wherein the trench pattern comprises a photoresist layer.
9. The method of claim 6 , further comprising, after removing the trench pattern and before removing the exposed portions of the etching stop layer and the diffusion barrier layer:
performing a cleaning process on the walls of the trench and the via hole.
10. A method comprising:
sequentially forming a diffusion barrier and an etching stop layer over a conductive layer, wherein the etching stop layer comprises SiOF;
forming an IMD layer directly on the etching stop layer, wherein the IMD layer comprises a first silane layer formed over the etching stop layer, a FSG layer formed over the first silane layer and a second silane layer formed over the FSG layer;
forming a via hole in the IMD layer to expose the etching stop layer;
forming a via filling layer in the via hole;
removing a portion of the via filling layer;
forming a trench pattern over the IMD layer and the via filling layer;
forming a trench by etching the IMD layer using the trench pattern as a mask;
removing the trench pattern;
removing the remaining portion of the via filling layer to expose the etching stop layer;
cleaning the walls of the trench and the via hole; and then
exposing the conductive layer by removing exposed portions of the etching stop layer and the diffusion barrier layer in the via hole.