IP Library Granted Patent US 8,039,386
Granted Patent B1
US 8,039,386 · App. 12/748,101 · Granted Oct 18, 2011

Method for forming a through silicon via (TSV)

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Quick Facts
Patent No.
US 8,039,386
App. No.
12/748,101
Granted
Oct 18, 2011
Kind
B1
Abstract

A method of forming a through silicon via includes forming a via opening in a substrate using a hard mask, wherein a polymer is formed in the via opening. A first wet clean removes a first portion of the polymer and forms a first carbon containing oxide along portions of the sidewalls. A first ash process modifies the first carbon containing oxide and removes a second portion of the polymer. A first wet etch removes the modified first carbon containing oxide and a third portion of the polymer. A second ash process forms a second carbon containing oxide along at least a portion of the sidewalls. A second wet etch process removes the second carbon containing oxide and a fourth portions of the polymer. A third ash process forms a third carbon containing oxide along portions of the sidewalls and removes any remaining portions of the polymer.

Claims (55)

1. A method of forming a through silicon via (TSV), the method comprising:

forming a hard mask over a semiconductor substrate, wherein the hard mask has a mask opening;

forming a via opening in the semiconductor substrate using the hard mask, wherein:

the via opening comprises a bottom and sidewalls;

a portion of the hard mask overhangs the via opening; and

a polymer comprising silicon, carbon, and fluorine is formed along at least a portion of the bottom of the via opening;

performing a first wet clean to remove a first portion of the polymer and form a first carbon containing oxide along portions of the sidewalls by pulling silicon and carbon from the substrate;

performing a first ash process to modify the first carbon containing oxide and to remove a second portion of the polymer;

performing a first wet etch process to remove the modified first carbon containing oxide and a third portion of the polymer;

performing a second ash process to form a second carbon containing oxide along at least a portion of the sidewalls by pulling silicon and carbon from the semiconductor substrate;

performing a second wet etch process to remove the second carbon containing oxide and a fourth portion of the polymer; and

performing a third ash process to form a third carbon containing oxide along portions of the sidewalls by pulling silicon and carbon from the substrate and removing any remaining portions of the polymer.

2. The method of claim 1 , wherein performing the first wet etch process further comprises etching the hard mask to make the mask opening larger.

3. The method of claim 2 , wherein performing the second wet etch process further comprises etching the hard mask to make the mask opening larger.

4. The method of claim 1 , further comprising forming an adhesive layer and conductive fill within the via opening.

5. The method of claim 4 , further comprising removing a portion of the semiconductor substrate.

6. The method of claim 1 , wherein the polymer is also formed along at least a portion of the sidewall of the via opening.

7. The method of claim 1 , wherein performing the first wet etch process and the second wet etch process comprise using dilute hydrofluoric acid.

8. The method of claim 1 , wherein performing a first wet clean comprises using piranha, hydrofluoric acid, and ammonium hydroxide.

9. The method of claim 1 , further comprising performing a second wet clean to remove the third carbon containing oxide and form a chemical oxide along the sidewalls and bottom of the via opening.

10. The method of claim 9 , wherein performing a second wet clean comprises using piranha, hydrofluoric acid, and ammonium hydroxide.

11. The method of claim 1 , wherein the hard mask comprises multiple layers.

12. The method of claim 1 , wherein the first, second and third carbon containing oxides comprise silicon and oxygen.

13. A method of forming a through silicon via (TSV), the method comprising:

forming a hard mask over a semiconductor substrate;

forming a via opening in the semiconductor substrate using the hard mask, wherein:

the via opening comprises a bottom and sidewalls; and

a polymer comprising silicon, carbon, and fluorine is formed along at least a portion of the bottom of the via opening;

performing a wet clean to remove a first portion of the polymer and form a first carbon containing oxide along portions of the sidewalls by pulling silicon and carbon from the substrate;

performing an ash process to remove a second portion of the polymer;

performing a wet process to remove a third portion of the polymer; and

repeating the steps of performing an ash process and performing a wet process a predetermined number of times;

forming an oxide along the sidewalls and bottom of the opening;

forming an adhesion layer and a conductive fill in the via opening; and

removing a portion of the semiconductor substrate.

14. The method of claim 13 , wherein the predetermined number of times is one time.

15. The method of claim 14 , wherein the hard mask has a mask opening and the first wet etch process further comprises etching the hard mask to make the mask opening larger.

16. The method of claim 15 , wherein performing the second wet etch process further comprises etching the hard mask to make the mask opening larger.

17. The method of claim 16 , wherein the polymer is formed along at least a portion of the sidewall of the via opening.

18. The method of claim 17 , wherein performing the first wet etch process and the second wet etch process comprise using dilute hydrofluoric acid.

19. The method of claim 18 , wherein forming an oxide along the sidewalls and bottom of the opening comprises performing a wet process.

20. A method of forming a through silicon via (TSV), the method comprising:

forming a hard mask over a semiconductor substrate;

forming a via opening in the semiconductor substrate using the hard mask, wherein:

the via opening comprises a bottom and sidewalls; and

a polymer comprising silicon, carbon, and fluorine is formed along at least a portion of the bottom of the via opening;

performing a first wet clean using piranha, hydrofluoric acid and ammonium hydroxide to remove a first portion of the polymer and form a first carbon containing oxide along portions of the sidewalls by pulling silicon and carbon from the substrate;

performing a first ash process to modify the first carbon containing oxide and to remove a second portion of the polymers;

performing a first wet etch process using dilute hydrofluoric acid to remove the modified first carbon containing oxide and a third portion of the polymer;

performing a second ash process to form a second carbon containing oxide along at least a portion of the sidewalls by pulling silicon and carbon from the semiconductor substrate;

performing a second wet etch process using dilute hydrofluoric acid to remove the second carbon containing oxide and a fourth portions of the polymer;

performing a third ash process to form a third carbon containing oxide along portions of the sidewalls by pulling silicon and carbon from the substrate and removing any remaining portions of the polymer;

performing a second wet clean piranha, hydrofluoric acid and ammonium hydroxide to remove the third carbon containing oxide and form a chemical oxide along the sidewalls and bottom of the via opening;

forming an adhesion layer and a conductive fill in the via opening; and

removing a portion of the semiconductor substrate.

Assignments (29)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073941/0814 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0745 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Jan 28, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CITIBANK, N.A.
Reel/Frame 041114/0044 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0027 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0866 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0120 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0194 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: INVENSAS CORPORATION
Reel/Frame 033093/0213 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2014
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUTOR, INC.
Reel/Frame 033134/0489 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2014
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 033134/0503 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Sep 3, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024933/0340 →
SECURITY AGREEMENT Recorded Sep 3, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024933/0316 →
SECURITY AGREEMENT Recorded Sep 1, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024915/0759 →
SECURITY AGREEMENT Recorded Sep 1, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024915/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2010
From: DAO, THUY B.; NOBLE, ROSS E.; TRIYOSO, DINA H.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 024148/0115 →