IP Library Granted Patent US 8,829,683
Granted Patent B2
US 8,829,683 · App. 13/852,322 · Granted Sep 9, 2014

Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,829,683
App. No.
13/852,322
Granted
Sep 9, 2014
Kind
B2
Abstract

A through via contains a conductor ( 244, 262 ) passing through a substrate ( 140 ). The substrate can be SOI or some other substrate containing two semiconductor layers ( 140.1, 140.2 ) on opposite sides of an insulating layer ( 140 B). The through via includes two constituent vias ( 144.1, 144.2 ) formed from respective different sides of the substrate by processes stopping on the insulating layer ( 140 B). Due to the insulating layer acting as a stop layer, high control over the constituent vias' depths is achieved. Each constituent via is shorter than the through via, so via formation is facilitated. The conductor is formed by separate depositions of conductive material into the constituent vias from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the through-via depth, so the deposition is facilitated. Other embodiments are also provided.

Claims (19)

1. A structure comprising:

a planar insulating layer;

a first semiconductor layer overlying the planar insulating layer, the first semiconductor layer having a planar bottom surface contacting a top surface of the planar insulating layer;

a second semiconductor layer underlying the planar insulating layer, the second semiconductor layer having a planar top surface contacting a bottom surface of the planar insulating layer;

one or more through vias each of which passes through the planar insulating layer and the first and second semiconductor layers;

wherein each through via's sidewall comprises:

a first semiconductor portion provided by the first semiconductor layer;

a second semiconductor portion provided by the second semiconductor layer; and

an insulator portion provided by the planar insulating layer;

wherein in at least one through via the insulating portion protrudes into the through via out of the first and second semiconductor portions.

2. The structure of claim 1 wherein in at least one trough via, the planar insulating layer protrudes into the through via out of the first and second semiconductor layers at each lateral position of the through via's sidewall.

3. The structure of claim 2 wherein each of the one or more through vias comprises a conductor which provides a conductive path between the first and second semiconductor layers.

4. The structure of claim 3 wherein at least one of the one or more through vias is filled with the respective conductor or with a combination of the respective conductor and an insulator provided between the conductor and the first semiconductor layer and/or between the conductor and the second semiconductor layer.

5. The structure of claim 1 wherein the first and second semiconductor layers have the same thickness at each through via.

6. The structure of claim 1 wherein for each through via,

1 /k*Th 2≦ Th 1≦ k*Th 2

wherein Th 1 is the thickness of the first semiconductor layer at the through via, Th 2 is the thickness of the second semiconductor layer at the through via, and k is a value greater than 1 but less than or equal to 10.

7. The method of claim 6 wherein k is less than or equal to 5.

8. The method of claim 6 wherein k is less than or equal to 3.

Assignments (7)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0745 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073941/0814 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2014
From: KOSENKO, VALENTIN; SAVASTIOUK, SERGEY
To: ALLVIA, INC.
Reel/Frame 034443/0204 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2014
From: ALLVIA, INC.
To: INVENSAS CORPORATION
Reel/Frame 034443/0242 →