IP Library Granted Patent US 9,698,131
Granted Patent B2
US 9,698,131 · App. 14/977,214 · Granted Jul 4, 2017

Methods of forming 3-D circuits with integrated passive devices

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Quick Facts
Patent No.
US 9,698,131
App. No.
14/977,214
Granted
Jul 4, 2017
Kind
B2
Abstract

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrates-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so the TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Claims (49)

1. A structure comprising circuitry for operation at one or more frequencies at least as high as a radio frequency, the circuitry comprising:

one or more active devices; and

one or more passive devices electrically coupled to the one or more active devices;

wherein the structure comprises:

a first semiconductor substrate comprising at least part of the one or more active devices;

a second semiconductor substrate overlying the first semiconductor substrate and supporting at least part of the one or more passive devices located over the second semiconductor substrate; and

a third semiconductor substrate located between the first and second semiconductor substrates;

wherein the circuitry further comprises one or more conductive paths passing through the second and third semiconductor substrates and electrically coupling the one or more passive devices to the one or more active devices;

wherein the third semiconductor substrate is a semiconductor material reducing electromagnetic coupling between the one or more passive devices and the one or more active devices at least at one of the one or more frequencies; and

wherein the second semiconductor substrate is a semiconductor material reducing electromagnetic coupling between the one or more passive devices and the one or more active devices at least at one of the one or more frequencies.

2. The structure of claim 1 wherein:

said at least part of the one or more active devices is spaced from a bottom of the first semiconductor substrate; and

the structure further comprises a heat sink attached to the bottom of the first semiconductor substrate.

3. The structure of claim 2 wherein the first semiconductor substrate is two or more times thinner than each of the second and third semiconductor substrates.

4. The structure of claim 1 wherein:

said at least part of the one or more active devices is located at a top of the first semiconductor substrate; and

the first semiconductor substrate is two or more times thinner than each of the second and third semiconductor substrates.

5. The structure of claim 4 further comprising a heat sink attached to a bottom of the first semiconductor substrate.

6. The structure of claim 1 wherein the circuitry is a power amplifier for operation at said one or more frequencies.

7. The structure of claim 1 wherein at least one said passive device comprises an element operating as a transmission line at least at one of the one or more frequencies, the transmission line comprising a first conductive strip and a second conductive strip, the first conductive strip overlying the second semiconductor substrate, the second conductive strip being between the second and third semiconductor substrates.

8. The structure of claim 1 wherein at least one said device comprises a first conductive strip and a second conductive strip, the first conductive strip overlying the second semiconductor substrate, the second conductive strip being between the second and third semiconductor substrates, the first and second conductive strips being a differential signal pair.

9. The structure of claim 1 wherein at least one said passive device comprises one or more inductor loops overlying the second semiconductor substrate.

10. The structure of claim 9 wherein said at least one said passive device comprising the one or more inductor loops also comprises a ground plane between the second and third semiconductor substrates, the ground plane being patterned, the ground plane being for reducing eddy current losses at least at one of the one or more frequencies.

11. The structure of claim 1 further comprising an electromagnetic band gap structure located between the second and third semiconductor substrates to enhance shielding of the first semiconductor substrate and said at least part of the one or more active devices from said at least part of the one or more passive devices at least at one of the one or more frequencies.

12. The structure of claim 1 wherein the semiconductor material of the third semiconductor substrate is at least as effective as a silicon material having a resistivity of at least 1000 ohm-cm in reducing the electromagnetic coupling between the one or more passive devices and the one or more active devices at least at said corresponding one of the one or more frequencies.

13. The structure of claim 1 wherein the semiconductor material of the second semiconductor substrate is at least as effective as a silicon material having a resistivity of at least 1000 ohm-cm in reducing the electromagnetic coupling between the one or more passive devices and the one or more active devices at least at said corresponding one of the one or more frequencies.

14. A method comprising operating, at one or more frequencies which are at least as high as a radio frequency, a circuitry comprising:

one or more active devices; and

one or more passive devices electrically coupled to the one or more active devices;

wherein at least part of the one or more active devices is located in a first semiconductor substrate;

at least part of the one or more passive devices is located over a second semiconductor substrate overlying the first semiconductor substrate; and

a third semiconductor substrate is located between the first and second semiconductor substrates;

wherein the circuitry comprises one or more conductive paths passing through the second and third semiconductor substrates and electrically coupling the one or more passive devices to the one or more active devices;

wherein the third semiconductor substrate is a semiconductor material reducing electromagnetic coupling between the one or more passive devices and the one or more active devices at least at one of the one or more frequencies; and

wherein the second semiconductor substrate is a semiconductor material reducing electromagnetic coupling between the one or more passive devices and the one or more active devices at least at one of the one or more frequencies.

15. The method of claim 14 wherein:

said at least part of the one or more active devices is spaced from a bottom of the first semiconductor substrate; and

a heat sink is attached to the bottom of the first semiconductor substrate.

16. The method of claim 15 wherein the first semiconductor substrate is two or more times thinner than each of the second and third semiconductor substrates.

17. The method of claim 14 wherein:

said at least part of the one or more active devices is located at a top of the first semiconductor substrate; and

the first semiconductor substrate is two or more times thinner than each of the second and third semiconductor substrates.

18. The method of claim 14 wherein the circuitry is a power amplifier.

19. The method of claim 14 wherein at least one said passive device comprises a transmission line comprising a first conductive strip and a second conductive strip, the first conductive strip overlying the second semiconductor substrate, the second conductive strip being between the second and third semiconductor substrates.

20. The method of claim 14 wherein at least one said device comprises a first conductive strip and a second conductive strip, the first conductive strip overlying the second semiconductor substrate, the second conductive strip being between the second and third semiconductor substrates, the first and second conductive strips being a differential signal pair.

21. The method of claim 14 wherein at least one said passive device comprises one or more inductor loops overlying the second semiconductor substrate, and also comprises a patterned ground plane between the second and third semiconductor substrates, the ground plane reducing eddy current losses.

22. The method of claim 14 further comprising an electromagnetic band gap structure located between the second and third semiconductor substrates and enhancing shielding of the first semiconductor substrate and said at least part of the one or more active devices from said at least part of the one or more passive devices.

23. The method of claim 14 wherein the semiconductor material of the third semiconductor substrate is at least as effective as a silicon material having a resistivity of at least 1000 ohm-cm in reducing the electromagnetic coupling between the one or more passive devices and the one or more active devices at least at said corresponding one of the one or more frequencies.

24. The method of claim 14 wherein the semiconductor material of the second semiconductor substrate is at least as effective as a silicon material having a resistivity of at least 1000 ohm-cm in reducing the electromagnetic coupling between the one or more passive devices and the one or more active devices at least at said corresponding one of the one or more frequencies.

Assignments (8)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0745 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073941/0814 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2017
From: SANDERS, PAUL W.; JONES, ROBERT E.; PETRAS, MICHAEL F.; RAMIAH, CHANDRASEKARAM
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 042048/0065 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 23, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 038084/0599 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: INVENSAS CORPORATION
Reel/Frame 038084/0801 →