Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory

1. A memory system comprising:

a memory array configured to store a plurality of data values and an associated plurality of error correction bits; and

a memory interface configured to support partial-word write operations to the memory array, wherein the memory interface is adapted to generate write check bits for the partial-word write operations in a predictive manner.

2. The memory system of claim 1 , wherein the memory interface comprises:

a read data path including a first error correction code (ECC) generator and means for generating a syndrome word in response to the error correction bits read from the memory array and error correction bits provided by the first ECC generator; and

a write path comprising a multiplexer circuit for merging a partial write data value with an uncorrected data value read from the memory array to create a merged write data word, and a second ECC generator coupled to receive the merged write data word.

3. The memory system of claim 2 , wherein the read data path is configured to operate in parallel with the write data path.

4. The memory system of claim 2 , wherein the read data path further comprises a partial syndrome decoder coupled to receive the syndrome word and a partial-word write enable signal, wherein the partial syndrome decoder is configured to generate a control signal that indicates whether a partial-word of the read data word containing an error is not being overwritten.

5. A method of performing a partial-word write transaction in a memory system implementing error code correction, the method comprising:

reading a first data word having a plurality of partial-words and a set of read check bits from an address of a memory;

determining that an error exists in the first data word, and identifying a partial-word of the first data word, which contains the error;

merging one or more partial-words of the first data word with one or more partial-words of a write data word, thereby creating a merged data word, wherein the merged data word contains the error;

generating a set of write check bits in response to the merged data word;

modifying the set of write check bits in response to the first data word and the set of read check bits, thereby creating a modified set of write check bits; and

writing the merged data word and the modified set of write check bits to the address of the memory.

6. The method of claim 5 , wherein the step of determining that an error exists in the first data word is performed in parallel with the steps of merging one or more partial-words of the first data word with one or more partial-words of a write data word and generating a set of write check bits in response to the merged data word.

7. A method of performing a partial-word write transaction in a memory system implementing error code correction, the method comprising:

reading a read data word and corresponding first set of read check bits from an address of a memory;

generating a second set of read check bits in response to the read data word;

generating a syndrome word in response to the first and second sets of read check bits, wherein the syndrome word identifies a location of an error, if any, in the read data word;

merging one or more partial-words of the read data word with one or more partial-words of a write data word, thereby creating a merged data word;

generating a first set of write check bits in response to the merged data word;

modifying the first set of write check bits to create a second set of write check bits if the merged data word includes a partial-word of the read data word which contains an error;

passing the first set of write check bits as the second set of write check bits if the merged data word does not include a partial-word of the read data word which contains an error; and

writing the merged data word and the second set of write check bits to the address of the memory.

8. The method of claim 7 , wherein the steps of generating the second set of read check bits and generating the syndrome word are performed in parallel with the steps of merging one or more partial-words of the read data word with one or more partial-words of the write data word and generating the first set of write check bits.

9. A method of performing a partial-word write transaction in a memory system implementing error code correction, the method comprising:

reading a first data word and a corresponding set of check bits from an address of a memory;

determining that an error exists in the first data word read from the memory;

merging one or more partial-words of the first data word with one or more partial-words of a write data word, thereby creating a merged data word, wherein the merged data word contains the error of the first data word;

generating a first set of write check bits in response to the merged data word;

generating a second set of write check bits in response to the first data word and the corresponding set of check bits;

modifying the first set of write check bits in response to the second set of write check bits, thereby creating a third set of write check bits; and

writing the merged data word and the third set of write check bits to the address of the memory.