Methods of forming 3-D circuits with integrated passive devices
View Patent ↗Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.
1. A method for forming a 3-D integrated circuit, comprising:
forming an active device (AD) substrate having an AD region thereon with device contacts therein;
forming an isolator substrate separately from the AD substrate and having one or more through-substrate-vias (TSVs) therein adapted to be coupled to one or more of the device contacts in the AD region of the AD substrate;
forming an integrated passive device (IPD) substrate separately from the AD substrate and the isolator substrate and having an IPD zone on its surface in which IPDs have been formed, and having a plurality of TSVs formed underlying the IPD zone through the IPD substrate, wherein the TSVs in the IPD substrate are coupled with the IPDs in the IPD zone, and at least some of the TSVs are adapted to couple one or more of the IPDs in the IPD zone to TSVs in the isolator substrate, and wherein at least some of the TSVs in the isolator substrate are vertically aligned with at least some of the TSVs in the IPD substrate; and
forming a further interconnect zone located between the isolator substrate and the IPD substrate, wherein the further interconnect zone includes a lateral conductor between two or more TSVs in a same substrate, thereby providing a connection selected from a group consisting of a cross-under connection between two or more IPDs in the IPD zone, and a cross-over connection between two or more device contacts of the AD substrate, and wherein at least one of the IPDs has a first element located in the IPD zone and a second element located in the further interconnect zone.
2. The method of claim 1 , wherein at least some of the TSVs in the isolator substrate are coupled to some of the device contacts in the AD region on the AD substrate.
3. The method of claim 1 , wherein some of the IPDs are coupled to other of the IPDs via the further interconnect zone.
4. The method of claim 1 , wherein the isolator substrate has a resistivity of 1000 ohm-cm or greater.
5. The method of claim 1 , wherein the isolator substrate has a thickness in a range of 10 and 200 micrometers or larger.
6. The method of claim 1 , wherein the IPD substrate has a resistivity of 1000 ohm-cm or greater.
7. The method of claim 1 , wherein the AD substrate has a first thickness, the isolator substrate has a second thickness, and the IPD substrate has a third thickness, and at least one or both of the second and third thickness are at least 2-20 times the first thickness.
8. The method of claim 1 , wherein the further interconnect zone includes an additional portion selected from a ground plane, and electrical shield, and an electromagnetic band gap structure.
9. The method of claim 1 , further comprising a circuit element, wherein a first portion of the circuit element is formed in the IPD zone, and a second portion of the circuit element is formed in the further interconnect zone, and wherein the circuit element is selected from an RF transmission line with first and second conductive strips, and an inductor with an inductor loop and a patterned ground plane.
10. A method of forming a 3-D integrated circuit, comprising:
forming an active device (AD) substrate having an AD region thereon with device contacts therein;
forming an isolator substrate separately from the AD substrate and having one or more through-substrate-vias (TSVs) therein adapted to be coupled to one or more of the device contacts in the AD region of the AD substrate;
forming an integrated passive device (IPD) substrate separately from the AD substrate and the isolator substrate and having an IPD zone on its surface in which IPDs have been formed, and having a plurality of TSVs formed underlying the IPD zone through the IPD substrate, wherein the TSVs in the IPD substrate are coupled with the IPDs in the IPD zone, and at least some of the TSVs are adapted to couple one or more of the IPDs in the IPD zone to TSVs in the isolator substrate;
forming a further interconnect zone located between the isolator substrate and the IPD substrate, wherein the further interconnect zone includes a lateral conductor between two or more TSVs in the IPD substrate, thereby providing a cross-under connection between two or more IPDs in the IPD zone; and
forming a circuit element, wherein a first portion of the circuit element is formed in the IPD zone, and a second portion of the circuit element is formed in the further interconnect zone.
11. The method of claim 10 , wherein the further interconnect zone includes a ground plane.
12. The method of claim 10 , wherein the further interconnect zone includes an electrical shield.
13. The method of claim 10 , wherein the further interconnect zone includes an electromagnetic band gap structure having one or more tuned elements.
14. The method of claim 10 , wherein the circuit element is an RF transmission line, the first portion of the circuit element is a first conductive strip of the RF transmission line, and the second portion of the circuit element is a second conductive strip of the RF transmission line.
15. The method of claim 14 , wherein the first conductive strip and the second conductive strip form a differential signal pair.
16. The method of claim 14 , wherein the second conductive strip is a ground.
17. The method of claim 10 , wherein the circuit element is an inductor, the first portion of the circuit element is an inductor loop, and the second portion is a patterned ground plane.