Patent Assignment
Reel/Frame 030258/0523
Supplement to Ip Security Agreement
Recorded: 2013-04-22
Pages: 17
Assignor
FREESCALE SEMICONDUCTOR, INC.
Executed: 2013-02-14
Assignee
CITIBANK, N.A., AS NOTES COLLATERAL AGENT
390 GREENWICH STREET, NEW YORK, NEW YORK, 10013
Covered Properties
(98)
Method and System for Automatically Controlling the Insertion of Control Word in CPRI Daisy Chain Configuration
Multiply and Accumulate Feedback
Split Gate Flash Cell
Integrated Circuit Device, Signal Processing System and Method for Managing Power Resources of a Signal Processing System
Application:
13/643,358 →
Publication:
US US20130054988A1
Opportunistic Cache Replacement Policy
Latent Slow Bit Detection for Non-Volatile Memory
Compiler Optimized Safety Mechanism
Method and System for Low Power Transmission and Data Alignment
Timing Event Generation Circuit for Mobile Communication Device
Processor Switchable Between Test and Debug Modes
Chip-Level Humidity Protection
Encapsulant for a Semiconductor Device
Application:
13/651,995 →
Electronic Circuits with Variable Attenuators and Methods of Their Operation
Patent:
8,674,746 →
Application:
13/653,155 →
Flexible Control Mechanism for Store Gathering in a Write Buffer
Resurf High Voltage Diode
High Voltage Diode
Dynamically Biased Output Structure
Amplifier Calibration
Patent:
8,653,890 →
Application:
13/656,551 →
Packaging for Semiconductor Sensor Devices and Methods
Packaged Integrated Circuit Having Large Solder Pads and Method for Forming
Via Placement and Electronic Circuit Design Processing Method and Electronic Circuit Design Utilizing Same
Patent:
8,595,667 →
Application:
13/661,131 →
Method of Making a Logic Transistor and a Non-Volatile Memory (Nvm) Cell
Methods and Structures for Capping a Structure with a Protective Coating
Patent:
8,637,393 →
Application:
13/661,377 →
Sram with Improved Write Operation
Semiconductor Device with Thermal Dissipation Lead Frame
Control Gate Word Line Driver Circuit for Multigate Memory
Production-Test Die Temperature Measurement
Sensor Single Track Trim Using Stationary Hardware and Fields
System and Method for Assigning a Message
Systems and Methods for Determining Aging Damage for Semiconductor Devices
Gate Driver with Desaturation Detection and Active Clamping
LDMOS Device with Minority Carrier Shunt Region
Methods and Integrated Circuit Package for Sensing Fluid Properties
Method and Apparatus for a Tunable Driver Circuit
Lcd Driver Verification System
Application:
13/665,902 →
Publication:
US US20140122010A1
Relaxation Oscillator
Memory Controller for Memory Device
Application:
13/665,906 →
Publication:
US US20140122775A1
Memory Device Redundancy Management System
System for Generating Gated Clock Signals
Patent:
8,643,411 →
Application:
13/665,921 →
Vector NCO and Twiddle Factor Generator
Delay Compensated Continuous Time Sigma Delta Analog-to-Digital Converter
Hardware-Based Memory Initialization
Semiconductor Device and Driver Circuit with an Active Device and Isolation Structure Interconnected Through a Diode Circuit, and Method of Manufacture Thereof
Semiconductor Device and Driver Circuit with an Active Device and Isolation Structure Interconnected Through a Resistor Circuit, and Method of Manufacture Thereof
Protection Device and Related Fabrication Methods
Offset Error Automatic Calibration Integrated Circuit
Wettable Lead Ends on a Flat-Pack No-Lead Microelectronic Package
Programming a Non-Volatile Memory (Nvm) System Having Error Correction Code (Ecc)
Trace Routing Within a Semiconductor Package Substrate
Integrated Circuit with Degradation Monitoring
Temperature Dependent Timer Circuit
Table Model Circuit Simulation Acceleration Using Model Caching
Dynamic Read Scheme for High Reliability High Performance Flash Memory
Non-Volatile Memory Robust Start-Up Using Analog-to-Digital Converter
Semiconductor Wafer Dicing Method
Application:
13/681,401 →
Publication:
US US20140024199A1
System and Method for Performing Scan Test
Semiconductor Device Package with Cap Element
Low-Power Voltage Tamper Detection
Flexible Control Mechanism for Store Gathering in a Write Buffer
Flexible Control Mechanism for Store Gathering in a Write Buffer
Integrated Circuit Electrical Protection Device
Trigger Circuit and Method for Improved Transient Immunity
Low Power Scan Flip-Flop Cell
System for Data Transfer Between Asynchronous Clock Domains
Test Structure Activated by Probe Needle
Electronic Devices with Cavity-Type, Permeable Material Filled Packages, and Methods of Their Manufacture
Voltage Ramp-Up Protection
Method and Integrated Circuit That Provides Tracking Between Multiple Regulated Voltages
Inertial Sensor and Method of Levitation Effect Compensation
Spring for Microelectromechanical Systems (Mems) Device
Application:
13/687,424 →
Publication:
US US20140144232A1
Electronic Devices with Embedded Die Interconnect Structures, and Methods of Manufacture Thereof
Semiconductor Device Package
Systems and Methods for Delivering Power in Response to a Connection Event
Systems and Methods for Controlling Power in Semiconductor Circuits
Methods for the Fabrication of Semiconductor Devices Including Sub-Isolation Buried Layers
Application:
13/689,274 →
Publication:
US US20140147985A1
Memory Column Drowsy Control
Providing an Automatic Optical Inspection Feature for Solder Joints on Semiconductor Packages
Patent:
8,535,982 →
Application:
13/689,424 →
Semiconductor Device Packages Providing Enhanced Exposed Toe Fillets
Application:
13/689,845 →
Publication:
US US20140151865A1
Over Voltage Protection for a Thin Oxide Load Circuit
Ac Coupled Level Shifter
Patent:
8,629,707 →
Application:
13/690,336 →
Random Access of a Cache Portion Using an Access Module
Integrated Circuit, Electronic Device and Esd Protection Therefor
Power Switching Apparatus and Method for Improving Current Sense Accuracy
Integrated Circuit Device, Electronic Device and Method for Detecting Timing Violations Within a Clock Signal
Embedded Logic Analyzer
Application:
13/709,049 →
Publication:
US US20130097462A1
Reducing the Power Consumption of Memory Devices
Integrated Circuits Including Integrated Passive Devices and Methods of Manufacture Thereof
Systems with Adjustable Sampling Parameters and Methods of Their Operation
Band Gap Reference Voltage Generator
System and Method for Cleaning Bond Wire
Application:
13/716,193 →
Publication:
US US20140110461A1
Rail to Rail Differential Buffer Input Stage
Multi-Voltage Domain Circuit Design Verification Method
Patent:
8,601,426 →
Application:
13/717,646 →
Semiconductor Package Signal Routing Using Conductive Vias
Reducing Mems Stiction by Introduction of a Carbon Barrier
Reducing Mems Stiction by Deposition of Nanoclusters
System for Optimizing Number of Dies Produced on a Wafer
Methods of Forming 3-D Circuits with Integrated Passive Devices
Method and System for Deblock Filtering Coded Macroblocks
Application:
13/682,751 →
Publication:
US US20140056363A1
Related Assignments
(24)
Other recorded transfers of the patents in this record — the chain of ownership.
Supplement to Ip Security Agreement
Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 030258/0540 →
Supplement to Ip Security Agreement
Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030258/0558 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0685 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0671 →
Patent Release
Jan 14, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037494/0312 →
Release of Security Interest
Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
Release of Security Interest
Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
Change of Name
Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
Merger
Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
Change of Name
Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
Merger
Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
Corrective Assignment to Correct the Nature of Conveyance Previously Recorded at Reel: 040652 Frame: 0241. Assignor(S) Hereby Confirms the Merger and Change of Name.
Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
Corrective Assignment to Correct the Nature of Conveyance Previously Recorded at Reel: 040626 Frame: 0683. Assignor(S) Hereby Confirms the Merger and Change of Name Effective November 7, 2016.
Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
Corrective Assignment to Correct the Nature of Conveyance Previously Recorded at Reel: 040632 Frame: 0001. Assignor(S) Hereby Confirms the Merger and Change of Name.
Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
Corrective Assignment to Correct the to Correct the Application No. from 13,883,290 to 13,833,290 Previously Recorded on Reel 041703 Frame 0536. Assignor(S) Hereby Confirms the the Assignment and Assumption of Security Interest in Patents..
Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
Release of Security Interest
Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
Release of Security Interest
Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 042985 Frame 0001. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 042762 Frame 0145. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 038017 Frame 0058. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 039361 Frame 0212. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
Corrective Assignment to Correct the Remove Application 11759915 and Replace It with Application 11759935 Previously Recorded on Reel 037486 Frame 0517. Assignor(S) Hereby Confirms the Assignment and Assumption of Security Interest in Patents.
Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
Corrective Assignment to Correct the Remove Application 11759915 and Replace It with Application 11759935 Previously Recorded on Reel 040928 Frame 0001. Assignor(S) Hereby Confirms the Release of Security Interest.
Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
Corrective Assignment to Correct the Remove Application 11759915 and Replace It with Application 11759935 Previously Recorded on Reel 040925 Frame 0001. Assignor(S) Hereby Confirms the Release of Security Interest.
Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →