Hardware-based memory initialization
View Patent ↗Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.
1. A method, comprising:
after completion of a Built-In-Self-Test (BIST) procedure in an integrated circuit including a first memory circuit, a second memory circuit, and a BIST circuit coupled to the first and second memory circuits, the BIST circuit further including a BIST controller, a sequencer circuit coupled to the BIST controller, and an address generator circuit, comparator circuit, and data generator circuit coupled to the sequencer circuit, and a Pseudo-Random Number Generator (PRNG) circuit coupled to the data generator circuit;
receiving, by the PRNG circuit, a seed state and generating a sequence of random logic values usable to initialize the first memory circuit in response to a Power-On-Reset (PoR) event as part of a memory initialization operation subsequent to a first BIST test performed upon the first memory circuit by the BIST circuit, wherein the initialization of the first memory circuit operation is invoked outside of any testing procedure of the first memory circuit and during normal operation of the first memory circuit; and
receiving, by the PRNG circuit, a different seed state and generating a different sequence of random logic values usable to initialize the second memory circuit as part of another memory initialization operation subsequent a second BIST test performed upon the second memory circuit by the BIST circuit, wherein the initialization of the second memory circuit operation is invoked outside of any testing procedure of the second memory circuit and during normal operation of the second memory circuit, wherein the BIST controller, sequencer circuit, address generator circuit, and data generator circuit are turned on during: the first BIST test, the second BIST test, and the memory initialization operations, and wherein the comparator circuit is turned on during the first and second BIST tests and turned off during the memory initialization operations.
2. The method of claim 1 , wherein the seed state is provided by another circuit external to the BIST circuit.
3. The method of claim 1 , wherein the seed state includes memory circuit identification stored in the memory circuit.
4. The method of claim 1 , wherein the seed state includes chip identification stored in another memory circuit of a same chip where the memory circuit is located.
5. The method of claim 1 , wherein the seed state includes timing or clock information.
6. The method of claim 1 , wherein the seed state includes information selected from the group consisting of: memory circuit identification and chip identification.
7. A method, comprising:
receiving a seed state;
generating a sequence of random logic values usable to initialize a first memory circuit in response to a Power-On-Reset (PoR) event as part of a memory initialization operation after completion of a first BIST test, wherein the initialization of the first memory circuit operation is invoked outside of any testing procedure of the first memory circuit and during normal operation of the first memory circuit;
after completion of a second BIST test performed upon the second memory circuit, receiving a different seed state; and
generating a different sequence of random logic values usable to initialize the second memory circuit as part of another memory initialization operation after completion of a second BIST test, wherein the initialization of the second memory circuit operation is invoked outside of any testing procedure of the second memory circuit and during normal operation of the second memory circuit, wherein the BIST circuit includes: a BIST controller, a sequencer, an address generator, a data generator, and a comparator, wherein the BIST controller, sequencer, address generator, and data generator are turned on during: the first BIST test, the second BIST test, and the memory initialization operations, and wherein the comparator is turned on during the first and second BIST tests and turned off during the memory initialization operations.
8. An integrated circuit, comprising:
a first memory circuit;
a second memory circuit; and
a Built-In-Self-Test (BIST) circuit coupled to the first and second memory circuits, the BIST circuit further comprising:
a BIST controller;
a sequencer circuit coupled to the BIST controller;
an address generator circuit, a comparator circuit, and a data generator circuit coupled to the sequencer circuit; and
a Pseudo-Random Number Generator (PRNG) circuit operably coupled to the data generator circuit, the PRNG circuit configured to receive a seed state and to generate a sequence of random logic values usable to initialize the first memory circuit in response to a Power-On-Reset (PoR) event as part of a memory initialization operation after completion of a first BIST test performed upon the first memory circuit by the BIST circuit, wherein the initialization of the first memory circuit operation is invoked outside of any testing procedure of the first memory circuit and during normal operation of the first memory circuit, the PRNG circuit further configured to receive a different seed state and to generate a different sequence of random logic values usable to initialize the second memory circuit as part of another memory initialization operation after completion of a second BIST test performed upon the second memory circuit by the BIST circuit, wherein the initialization of the second memory circuit operation is invoked outside of any testing procedure of the second memory circuit and during normal operation of the second memory circuit, wherein the BIST controller, sequencer circuit, address generator circuit, and data generator circuit are turned on during: the first BIST test, the second BIST test, and the memory initialization operations, and wherein the comparator circuit is turned on during the first and second BIST tests and turned off during the memory initialization operations.
9. The integrated circuit of claim 8 , the PRNG circuit configured to receive the seed state from at least one of: the first memory circuit, the second memory circuit, or another memory circuit.
10. The integrated circuit of claim 8 , the PRNG circuit configured to receive a different seed state and to generate a different sequence of random logic values usable to re-initialize the first memory circuit after the initialization.
11. The integrated circuit of claim 8 , the PRNG circuit configured to receive a different seed state and to generate a different sequence of random logic values usable to initialize another memory circuit within the integrated circuit subsequently to another BIST test performed upon the other memory circuit by the BIST circuit.
12. The integrated circuit of claim 8 , wherein the BIST tests are part of the integrated circuit's production.
13. The integrated circuit of claim 8 , wherein the BIST tests are part of the integrated circuit's in-field operation.