IP Library › Assignment 041414/0883
Patent Assignment
Reel/Frame 041414/0883

CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016.

Recorded: 2017-01-12 Received: 2017-01-12 Pages: 39
Assignors
Assignee
NXP USA, INC.
6501 WILLIAM CANNON DRIVE WEST, AUSTIN, TX, 78735, UNITED STATES
Covered Applications (100)
WIRELESS POWER TRANSMITTERS WITH WIDE INPUT VOLTAGE RANGE AND METHODS OF THEIR OPERATION
App. No. 15/344,250
→
MONOLITHIC MICROWAVE INTEGRATED CIRCUITS
App. No. 15/344,174
→
PHASE SHIFT AND ATTENUATION CIRCUITS FOR USE WITH MULTIPLE-PATH AMPLIFIERS
App. No. 15/344,304
→
ESD PROTECTION STRUCTURE
App. No. 15/344,131
→
COMMUNICATON UNIT RECEIVER, INTEGRATED CIRCUIT AND METHOD FOR ADC DYNAMIC RANGE SELECTION
App. No. 15/342,274
→
Amplifier Architecture Reconfiguration
App. No. 15/342,637
→
COMMUNICATON UNIT, CIRCUIT FOR QUADRATURE SAMPLING ERROR ESTIMATION AND COMPENSATION AND METHOD THEREFOR
App. No. 15/342,198
→
PROGRAMMABLE RESISTIVE ELEMENTS AS VARIABLE TUNING ELEMENTS
App. No. 15/340,729
→
METHOD AND APPARATUS FOR CALIBRATING A DIGITALLY CONTROLLED OSCILLATOR
App. No. 15/340,513
→
SEMICONDUCTOR DEVICE WITH ENHANCED 3D RESURF
App. No. 15/340,848
→
SYSTEMS AND METHODS FOR DETECTING CHANGE IN SPECIES IN AN ENVIRONMENT
App. No. 15/337,887
→
METHOD AND APPARATUS FOR DATA SET CLASSIFICATION BASED ON GENERATOR FEATURES
App. No. 15/334,920
→
RADIO FREQUENCY COUPLING AND TRANSITION STRUCTURE
App. No. 15/334,922
→
Multi-Bit Data Flip-Flop With Scan Initialization
App. No. 15/299,551
→
OUTPUT IMPEDANCE MATCHING CIRCUIT FOR RF AMPLIFIER DEVICES, AND METHODS OF MANUFACTURE THEREOF
App. No. 15/331,115
→
PACKAGE MATERIALS MONITOR AND METHOD THEREFOR
App. No. 15/298,368
→
METHOD AND APPARATUS FOR PERFORMING DISTRIBUTED COMPUTATION OF PRECODING ESTIMATES
App. No. 15/299,041
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SEMICONDUCTOR DEVICE HAVING A PROTECTIVE MATERIAL WITH A FIRST pH FORMED AROUND COOPER WIRE BONDS AND ALUMINUM PADS FOR NEUTRALIZES A SECOND pH OF AN OUTER ENCAPSULANT MATERIAL
App. No. 15/298,743
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MICROELECTRONIC PACKAGES HAVING AXIALLY-PARTITIONED HERMETIC CAVITIES AND METHODS FOR THE FABRICATION THEREOF
App. No. 15/298,657
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LIGHT-WEIGHT KEY UPDATE MECHANISM WITH BLACKLISTING BASED ON SECRET SHARING ALGORITHM IN WIRELESS SENSOR NETWORKS
App. No. 15/297,356
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Autonomous Key Update Mechanism with Blacklisting of Compromised Nodes for Mesh Networks
App. No. 15/297,332
→
FEEDBACK DIRECTED PROGRAM STACK OPTIMIZATION
App. No. 15/297,606
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TONE REJECTION DURING SYNCHRONIZATION IN FREQUENCY SHIFT KEYED MODULATION SYSTEMS
App. No. 15/283,473
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DISTRIBUTED RESERVATION BASED COHERENCY PROTOCOL
App. No. 15/280,383
→
METHOD FOR LINK ADAPTATION AND POWER AMPLIFIER VOLTAGE CONTROL AND SYSTEM THEREFOR
App. No. 15/279,610
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OPERATION AMPLIFIERS WITH OFFSET CANCELLATION
App. No. 15/278,934
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SMALL SIGNAL INPUT BUFFER
App. No. 15/278,166
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CONFIGURATION OF DEFAULT VOLTAGE LEVEL FOR DUAL-VOLTAGE INPUT/OUTPUT PAD CELL VIA VOLTAGE RAIL RAMP UP TIMING
App. No. 15/269,475
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SYSTEM AND METHOD FOR ADJUSTING BOOT INTERFACE FREQUENCY
App. No. 15/268,639
→
AIR CAVITY PACKAGES AND METHODS FOR THE PRODUCTION THEREOF
App. No. 15/269,629
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Compiler Global Memory Access Optimization In Code Regions Using Most Appropriate Base Pointer Registers
App. No. 15/267,835
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SEMICONDUCTOR PACKAGE HAVING AN ISOLATION WALL TO REDUCE ELECTROMAGNETIC COUPLING
App. No. 15/267,455
→
SYSTEMS AND METHODS FOR DYNAMICALLY ASSIGNING DOMAIN IDENTIFIERS FOR ACCESS CONTROL
App. No. 15/264,865
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CIRCUIT AND METHOD FOR TESTING FLIP FLOP STATE RETENTION
App. No. 15/264,958
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REFERENCE VOLTAGE GENERATOR
App. No. 15/264,558
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COMMUNICATION LINK ADJUSTMENTS IN WIRELESS NETWORKS BASED UPON COMPOSITE LQI MEASUREMENTS
App. No. 15/260,926
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SEMICONDUCITIVE CATECHOL GROUP ENCAPSULANT ADHESION PROMOTER FOR A PACKAGED ELECTRONIC DEVICE
App. No. 15/256,801
→
DATA CLUSTERING EMPLOYING MAPPING AND MERGING
App. No. 15/256,633
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SINGLE INDUCTOR, MULTIPLE OUTPUT DC-DC CONVERTER
App. No. 15/256,575
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INTEGRATED CIRCUIT USING STANDARD CELLS FROM TWO OR MORE LIBRARIES
App. No. 15/256,592
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SYSTEM AND METHOD FOR REDUCING HIBERNATE AND RESUME TIME
App. No. 15/256,615
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PROTECTING EMBEDDED NONVOLATILE MEMORY FROM INTERFERENCE
App. No. 15/256,591
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SUBSTRATE ARRAY FOR PACKAGING INTEGRATED CIRCUITS
App. No. 15/256,573
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RAIL-TO-RAIL COMPARATOR WITH SHARED ACTIVE LOAD
App. No. 15/256,571
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INTEGRATED CIRCUIT WITH LOW POWER SCAN SYSTEM
App. No. 15/256,618
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LOW POWER STATE RETENTION MODE FOR PROCESSOR
App. No. 15/256,589
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APPARATUS AND METHOD FOR PLACING STRESSORS WITHIN AN INTEGRATED CIRCUIT DEVICE TO MANAGE ELECTROMIGRATION FAILURES
App. No. 15/256,207
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MUTUAL CAPACITANCE SENSING CIRCUIT WITH INCREASED SENSITIVITY
App. No. 15/253,906
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POWER AMPLIFIER SYSTEM WITH INTEGRATED ANTENNA
App. No. 15/254,227
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SLAVE DEVICE ALERT SIGNAL IN INTER-INTEGRATED CIRCUIT (I2C) BUS SYSTEM
App. No. 15/254,962
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Power Switch Module, Smart Grid Power Supply Arrangement and Method Therefor
App. No. 15/254,525
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TESTING MULTI-CORE INTEGRATED CIRCUIT WITH PARALLEL SCAN TEST DATA INPUTS AND OUTPUTS
App. No. 15/254,993
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METHODS AND SENSOR DEVICES FOR SENSING FLUID PROPERTIES
App. No. 15/252,621
→
INTEGRATED CIRCUITS AND METHODS FOR DYNAMIC ALLOCATION OF ONE-TIME PROGRAMMABLE MEMORY
App. No. 15/253,023
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SCAN CIRCUITRY WITH IDDQ VERIFICATION
App. No. 15/252,577
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PROTECTED SENSOR FIELD EFFECT TRANSISTORS
App. No. 15/251,141
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METHODS OF FABRICATING COMPLEMENTARY GALLIUM NITRIDE INTEGRATED CIRCUITS
App. No. 15/251,114
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TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) WITH MAGNETIC TUNNEL JUNCTION (MTJ) DEVICES
App. No. 15/251,996
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MULTIPROCESSING SYSTEM WITH PERIPHERAL POWER CONSUMPTION CONTROL
App. No. 15/248,896
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ELECTRONIC DEVICES WITH SEMICONDUCTOR DIE ATTACHED WITH SINTERED METALLIC LAYERS, AND METHODS OF FORMATION OF SUCH DEVICES
App. No. 15/247,393
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INTEGRATED CIRCUIT DEVICES WITH COUNTER-DOPED CONDUCTIVE GATES
App. No. 15/246,262
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ALUMINUM NITRIDE PROTECTION OF SILVER APPARATUS, SYSTEM AND METHOD
App. No. 15/244,922
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METHODS AND SYSTEMS FOR ELECTRICALLY CALIBRATING TRANSDUCERS
App. No. 15/243,767
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LATERALLY DIFFUSED MOSFET WITH ISOLATION REGION
App. No. 15/242,322
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SOFT ERROR DETECTION IN A MEMORY SYSTEM
App. No. 15/239,563
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AMPLFIERS AND RELATED INTEGRATED CIRCUITS
App. No. 15/237,015
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METHOD FOR PERFORMING DATA TRANSACTION THAT SELECTIVELY ENABLES MEMORY BANK CUTS AND MEMORY DEVICE THEREFOR
App. No. 15/236,459
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AUTOMATIC MEMORY SECURITY
App. No. 15/235,069
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HANDLING DEFECTIVE NON-VOLATILE MEMORY
App. No. 15/235,084
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WIRELESS CHARGER USING FREQUENCY ALIASING FSK DEMODULATION
App. No. 15/235,081
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INPUT BUFFER WITH SELECTABLE HYSTERESIS AND SPEED
App. No. 15/235,074
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OSCILLATOR CIRCUIT
App. No. 15/231,916
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SAMPLE AND HOLD CIRCUIT
App. No. 15/231,946
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SWITCHING POWER CONVERTER
App. No. 15/231,981
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MULTI-BIT FLIP-FLOP WITH SHARED CLOCK SWITCH
App. No. 15/230,459
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VIDEO ENCODER WITH ADJUSTABLE INTRA-REFRESH RATE
App. No. 15/230,457
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DEVICES WITH SIGNAL CHARACTERISTIC DEPENDENT CONTROL CIRCUITRY AND METHODS OF OPERATION THEREFOR
App. No. 15/229,312
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SYMMETRICAL POSITIVE AND NEGATIVE REFERENCE VOLTAGE GENERATION
App. No. 15/227,032
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TRANSISTOR WITH CHARGE ENHANCED FIELD PLATE STRUCTURE AND METHOD
App. No. 15/224,791
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CLEAR CHANNEL ASSESSMENT
App. No. 15/224,891
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ADAPTABLE SENSE CIRCUITRY AND METHOD FOR READ-ONLY MEMORY
App. No. 15/223,213
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DIGITAL PREDISTORTION FOR A POWER AMPLIFIER AND METHOD THEREFOR
App. No. 15/222,735
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SYSTEM AND METHOD FOR LINEARITY CALIBRATION IN MIXED-SIGNAL DEVICES
App. No. 15/221,286
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METHODS FOR REPACKAGING COPPER WIRE-BONDED MICROELECTRONIC DIE
App. No. 15/221,372
→
ANALOG-TO-DIGITAL CONVERSION WITH LINEARITY CALIBRATION
App. No. 15/221,317
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SYSTEM AND METHOD FOR MAPPING CONTROL AND USER DATA
App. No. 15/218,053
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Semiconductor Structure With Sacrificial Anode and Method for Forming
App. No. 15/215,037
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AUTONOMOUS HARDWARE FOR APPLICATION POWER USAGE OPTIMIZATION
App. No. 15/214,599
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LOW VARIATION POWER-ON-RESET CIRCUIT
App. No. 15/214,336
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HETEROGENEOUS MULTI-PROCESSOR DEVICE AND METHOD OF ENABLING COHERENT DATA ACCESS WITHIN A HETEROGENEOUS MULTI-PROCESSOR DEVICE
App. No. 15/213,875
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LOW-DROPOUT REGULATOR WITH POLE-ZERO TRACKING FREQUENCY COMPENSATION
App. No. 15/213,606
→
SCHEDULER FOR LAYER MAPPED CODE WORDS
App. No. 15/213,364
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SYSTEMS AND METHODS FOR NON-VOLATILE FLIP FLOPS
App. No. 15/212,826
→
BREACH DETECTION IN INTEGRATED CIRCUITS
App. No. 15/210,567
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Method of Integrating a Copper Plating Process in a Through-Substrate-Via (TSV) on CMOS Wafer
App. No. 15/209,964
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Sample-and-Hold Circuit
App. No. 15/209,573
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MEMORY CONTROLLER FOR PERFORMING WRITE TRANSACTION WITH STALL WHEN WRITE BUFFER IS FULL AND ABORT WHEN TRANSACTION SPANS PAGE BOUNDARY
App. No. 15/207,506
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INSTRUCTION PRE-FETCHING
App. No. 15/202,105
→
HARDWARE CONTROLLED INSTRUCTION PRE-FETCHING
App. No. 15/202,160
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SYSTEM AND METHOD FOR MONITORING VOLTAGE ACROSS ISOLATION BARRIER
App. No. 15/198,651
→