IP Library Granted Patent US 9,857,329
Granted Patent B2
US 9,857,329 · App. 15/251,141 · Granted Jan 2, 2018

Protected sensor field effect transistors

Inventors: Patrice M. Parris (Phoenix, AZ); Weize Chen (Phoenix, AZ); Richard J. de Souza (Chandler, AZ); Jose Fernandez Villasenor (Tokyo, JP); Md M. Hoque (Gilbert, AZ); David E. Niewolny (Austin, TX); Raymond M. Roop (Paradise Valley, AZ)
Assignee: NXP USA, Inc.
G01N27/4148B01L3/50273B01L3/502715G01N27/28G01N27/414H01L21/67259H01L29/66431B01L3/5027B01L2200/10B01L2200/12B01L2300/04B01L2300/041B01L2300/0645B01L2300/0887B01L2400/0415B01L2400/0418H01L29/66462H01L31/119
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Quick Facts
Patent No.
US 9,857,329
App. No.
15/251,141
Granted
Jan 2, 2018
Kind
B2
Abstract

Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.

Claims (37)

1. A sensor field effect transistor (SFET), comprising:

a semiconductor substrate;

a field effect transistor supported by the semiconductor substrate and comprising a source, a drain, and a gate;

a sense electrode supported by the semiconductor substrate and in electrical communication with the gate;

an enclosed analyte channel that is supported by the semiconductor substrate, is configured to contain an analyte fluid and to permit fluid contact between the analyte fluid and the sense electrode, extends in contact with the sense electrode, and extends between an analyte inlet and an analyte outlet, wherein the analyte inlet and the analyte outlet are spaced apart from the sense electrode along a length of the enclosed analyte channel; and

a microfluidic separation structure supported by the semiconductor substrate and configured to separate at least one component of the analyte fluid from at least one other component of the analyte fluid prior to fluid contact between the analyte fluid and the sense electrode.

2. The SFET of claim 1 , further comprising a microfluidic drive structure supported by the semiconductor substrate and configured to provide a motive force for flow of the analyte fluid through the enclosed analyte channel.

3. The SFET of claim 2 , wherein the microfluidic drive structure comprises an electroosmotic drive structure.

4. The SFET of claim 3 , wherein the electroosmotic drive structure comprises a plurality of electrical lines formed across the enclosed analyte channel.

5. The SFET of claim 1 , wherein the sense electrode forms a portion of the gate.

6. The SFET of claim 1 , wherein the sense electrode is spaced apart from the gate and in electrical communication with the gate via an electrode conductor.

7. The SFET of claim 1 , further comprising an overlying layer, which is supported by the semiconductor substrate, a trench, which extends within the overlying layer and bounds at least a first portion of the enclosed analyte channel, and a cover structure, which is supported by the overlying layer and extends across a portion of an opening of the trench that is opposed to the sense electrode to bound at least a second portion of the enclosed analyte channel.

8. The SFET of claim 1 , wherein the SFET comprises:

a plurality of spaced apart enclosed analyte channels, wherein

each of the plurality of spaced apart enclosed analyte channels extends between a respective analyte inlet and a respective analyte outlet, and

each of the plurality of spaced apart enclosed analyte channels extends in contact with the sense electrode.

9. The SFET of claim 1 , wherein the SFET comprises:

a plurality of spaced apart enclosed analyte channels; and

a plurality of sense electrodes, wherein

each of the plurality of spaced apart enclosed analyte channels extends between a respective analyte inlet and a respective analyte outlet,

each of the plurality of spaced apart enclosed analyte channels extends in contact with a respective sense electrode of the plurality of sense electrodes, and

each of the plurality of sense electrodes is in electrical communication with the gate.

10. A method of fabricating a sensor field effect transistor (SFET), the method comprising:

forming a field effect transistor, wherein the field effect transistor comprises a source, a drain, and a gate and is supported by a semiconductor substrate;

forming a sense electrode, wherein the sense electrode is in electrical communication with the gate and is supported by the semiconductor substrate;

forming an overlying layer, wherein the overlying layer is in contact with the sense electrode and is supported by the semiconductor substrate;

forming an analyte-receiving region, which is configured to contain an analyte fluid, within the overlying layer, wherein the analyte-receiving region extends in contact with the sense electrode and permits fluid contact between the analyte fluid and the sense electrode;

forming a microfluidic separation structure on the semiconductor substrate, wherein the microfluidic separation structure is configured to separate at least one component of the analyte fluid from at least one other component of the analyte fluid when the analyte fluid flows through an enclosed analyte channel that comprises the analyte-receiving region; and

placing a cover structure, which at least partially encloses the analyte-receiving region, on the semiconductor substrate.

11. The method of claim 10 , wherein the placing the cover structure comprises attaching a pre-formed cover structure to the overlying layer.

12. The method of claim 10 , wherein the placing the cover structure comprises performing a non-conformal deposition to deposit a cover material at least partially within the analyte-receiving region and to at least partially enclose the analyte-receiving region.

13. The method of claim 10 , wherein the placing the cover structure comprises placing a soluble cover material that is soluble in the analyte fluid.

14. The method of claim 10 , wherein the method comprises forming a microfluidic drive structure on the semiconductor substrate, wherein the microfluidic drive structure is configured to provide a motive force for flow of the analyte fluid between an analyte inlet and an analyte outlet of an enclosed analyte channel that comprises the analyte-receiving region.

15. The method of claim 10 , wherein the forming the sense electrode comprises forming the sense electrode at least partially concurrently with the forming the field effect transistor.

16. The method of claim 10 , wherein the forming the sense electrode comprises forming the sense electrode subsequent to the forming the field effect transistor.

17. The method of claim 10 , wherein the forming the overlying layer comprises forming the overlying layer on the semiconductor substrate and such that the overlying layer covers the sense electrode.

18. The method of claim 17 , wherein the forming the analyte-receiving region includes removing a portion of the overlying layer, and further wherein the placing the cover structure includes placing the cover structure on the overlying layer such that the overlying layer extends between the cover structure and the semiconductor substrate.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2016
From: PARRIS, PATRICE M.; CHEN, WEIZE; DE SOUZA, RICHARD J.; VILLASENOR, JOSE FERNANDEZ; HOQUE, MD M.; NIEWOLNY, DAVID E.; ROOP, RAYMOND M.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 039582/0152 →
Continuity (2)
Continuation 14731795 · Jun 5, 2015
Related Publication 20160370314A1 · Dec 22, 2016