Integrated circuit with low power scan system

1. An integrated circuit operable in a functional mode and a scan mode, comprising:

at least one scan chain formed by a plurality of cascaded flip-flop cells, wherein the scan chain receives a scan input signal (SI), and outputs a scan output signal (SO), and wherein each flip-flop cell comprises:

a master latch that receives a first data signal and generates a first latch signal based on a clock signal;

a slave latch, connected to the master latch, that receives the first latch signal and generates a second latch signal based on the clock signal;

a first multiplexer having first and second input terminals respectively connected to the master and slave latches for receiving a first input signal and the second latch signal, and generating a scan data output signal (SDO) depending on a trig signal, wherein the first input signal is one of the first data signal and the first latch signal; and

a first logic gate that gates the clock signal provided to the slave latch with the trig signal,

wherein the plurality of flip-flop cells include at least a first flip-flop cell that receives the scan input signal, and a last flip-flop cell that outputs the scan output signal; and

a control unit connected to the scan chain that successively asserts the trig signal to each of the plurality of flip-flop cells in the scan mode, wherein the control unit comprises:

a counter that receives the clock signal and generates a counting signal based on the clock signal, wherein the counter is reset by a scan enable signal in the functional mode;

a decoder connected to the counter that receives the counting signal and generates a one-hot signal for successively asserting the trig signal to each of the flip-flop cells in the scan chain in the scan mode; and

a plurality of second logic gates connected to the decoder, each second logic gate for gating a corresponding bit of the one-hot signal based on the scan enable signal.

2. The integrated circuit of claim 1 , wherein each flip-flop cell further comprises:

a second multiplexer, connected to the master latch, that receives a data input signal (D) and a scan data input signal (SDI), and generates the first data signal depending on the scan enable signal that is active in the scan mode.

3. The integrated circuit of claim 1 , wherein the trig signal to each of the flip-flop cells is asserted successively from the trig signal to the last flip-flop cell to the trig signal to the first flip-flop cell.

4. The integrated circuit of claim 1 , wherein the counter is triggered at a leading edge of a second half of each clock cycle.

5. The integrated circuit of claim 1 , wherein the second logic gate comprises an OR gate, and each bit of the one-hot signal is gated by an inverse scan enable signal.

6. The integrated circuit of claim 3 , wherein the at least one scan chain comprises a plurality of scan chains that form an array of the flip-flop cells, wherein the array comprises a plurality of columns of the flip-flop cells including at least a first column formed by the first flip-flop cells of each of the scan chains, and a last column formed by the last flip-flop cells of each of the scan chains, wherein the flip-flop cells of each column share a common column trig signal provided by the control unit, and wherein the column trig signal of each of the columns is asserted successively from the column trig signal of the last column to the column trig signal of the first column in the scan mode.

7. The integrated circuit of claim 1 , wherein the first logic gate comprises an AND gate.

8. The integrated circuit of claim 1 , wherein the master latch receives the first data signal and generates the first latch signal in a second half of each clock cycle, and the slave latch receives the first latch signal and generates the second latch signal in a first half of a next clock cycle.