IP Library Granted Patent US 9,785,177
Granted Patent B1
US 9,785,177 · App. 15/227,032 · Granted Oct 10, 2017

Symmetrical positive and negative reference voltage generation

Inventors: Ricardo Coimbra (Campinas, BR); Javier Mauricio Olarte Gonzalez (Campinas, BR)
Assignee: NXP USA, Inc.
G05F3/16H03F3/45475H03F2200/165H03F2203/45248H03F2203/45288
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Quick Facts
Patent No.
US 9,785,177
App. No.
15/227,032
Granted
Oct 10, 2017
Kind
B1
Abstract

In an embodiment, an electronic device includes a first amplifier having a non-inverting input configured to receive a reference voltage and an inverting input coupled to a first output node, where the first amplifier is configured to produce a first output voltage at the first output node. The electronic device also includes a second amplifier having a non-inverting input coupled to a ground reference level, and an inverting input coupled to the first output node via a first resistor and to a second output node via a second resistor, where the second amplifier is configured to produce a second output voltage at the second output node.

Claims (29)

1. An electronic device, comprising:

a first amplifier having a non-inverting input configured to receive a reference voltage and an inverting input coupled to a first output node, wherein the first amplifier is configured to produce a first output voltage at the first output node;

a second amplifier having a non-inverting input coupled to a ground reference level, and an inverting input coupled to the first output node via a first resistor and to a second output node via a second resistor, wherein the second amplifier is configured to produce a second output voltage at the second output node, wherein the reference voltage is selected via a multiplexer coupled to a resistor ladder, and wherein the resistor ladder is coupled to a reference current source or to a reference voltage source; and

a low-pass filter coupled to the multiplexer and to the non-inverting input of the first amplifier.

2. The electronic device of claim 1 , wherein the first amplifier has a first stage configured to output a maximum current at an intermediary node.

3. An electronic device, comprising:

a first amplifier having a non-inverting input configured to receive a reference voltage and an inverting input coupled to a first output node, wherein the first amplifier is configured to produce a first output voltage at the first output node;

a second amplifier having a non-inverting input coupled to a ground reference level, and an inverting input coupled to the first output node via a first resistor and to a second output node via a second resistor, wherein the second amplifier is configured to produce a second output voltage at the second output node,

wherein the first amplifier has a first stage configured to output a maximum current at an intermediary node, and wherein the first amplifier further includes a capacitor coupled to the intermediary node and to the ground reference level.

4. The electronic device of claim 3 , further comprising a buffer stage coupled to the intermediary node.

5. The electronic device of claim 3 , wherein in response to a positive step change in the reference voltage, the first output voltage increases at a first rate given by a ratio between the maximum current and a capacitance presented by the capacitor.

6. The electronic device of claim 5 , wherein the second output voltage decreases with a second rate having a magnitude equal to the first rate.

7. A dual-reference voltage source, comprising:

a first amplifier configured to produce a first reference voltage at a first output node with a first slew rate;

a second amplifier coupled to the first output node and configured to produce a second reference voltage at a second output node with a second slew rate having a magnitude equal to the first slew rate, wherein the second reference voltage is symmetric with respect to the first reference voltage, wherein the first amplifier has a non-inverting input configured to receive a selected voltage and an inverting input coupled to the first output node, wherein the selected voltage is selected via a multiplexer coupled to a resistor ladder, and wherein the resistor ladder is coupled to a reference current source or to a reference voltage source; and

a low-pass filter coupled to the multiplexer and to the non-inverting input of the first amplifier.

8. The dual-reference voltage source of claim 7 , wherein the second amplifier has a non-inverting input coupled to a ground reference level, and an inverting input coupled to the first output node via a first resistor and to the second output node via a second resistor.

9. The dual-reference voltage source of claim 7 , wherein the first amplifier has a first stage configured to output a maximum output current at an intermediary node.

10. A dual-reference voltage source, comprising:

a first amplifier configured to produce a first reference voltage at a first output node with a first slew rate;

a second amplifier coupled to the first output node and configured to produce a second reference voltage at a second output node with a second slew rate having a magnitude equal to the first slew rate, wherein the second reference voltage is symmetric with respect to the first reference voltage, wherein the first amplifier has a non-inverting input configured to receive a selected voltage and an inverting input coupled to the first output node, wherein the first amplifier has a first stage configured to output a maximum output current at an intermediary node, and wherein the first amplifier further includes a capacitor coupled to the intermediary node and to the ground reference level.

11. The dual-reference voltage source of claim 10 , wherein, in response to a change in the selected voltage, the first reference voltage changes with the first slew rate given by a ratio between the maximum output current and a capacitance of the capacitor.

12. The dual-reference voltage source of claim 11 , wherein the second reference voltage changes in the opposite direction with a second slew rate having a magnitude equal to the first slew rate.

13. A method, comprising:

receiving, at a non-inverting input of a first amplifier, a reference voltage, wherein the first amplifier has an inverting input coupled to a first output node;

producing a first output voltage at the first output node; and

producing a second output voltage symmetric with respect to the first output voltage at a second output node of a second amplifier, wherein the second amplifier has a non-inverting input coupled to a ground reference level, and an inverting input coupled to the first output node via a first resistor and to the second output node via a second resistor,

wherein the first amplifier has a first stage configured to output a maximum output current at an intermediary node, wherein the first amplifier further includes a capacitor coupled to the intermediary node and to the ground reference level, and wherein in response to a change in the selected voltage, the first reference voltage increases with a slew rate given by a ratio between the maximum output current and a capacitance of the capacitor.

14. The method of claim 13 , wherein the first resistor has a first resistance and the second resistor has a second resistance, and wherein a ratio between the first and second resistances is proportional to a ratio between the magnitudes of the first and second output voltages.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2016
From: COIMBRA, RICARDO; GONZALEZ, JAVIER MAURICIO OLARTE
To: NXP B.V.
Reel/Frame 039325/0868 →