Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures
An integrated circuit device includes a first line in a first metal layer of the integrated circuit device, wherein the first line forms at least a portion of an interconnect, a second line in a second metal layer of the integrated circuit device, and a first via that couples the first line to the second line. The integrated circuit device further includes a first stressor disposed at a first area of the interconnect, wherein the first area at least partially overlaps the first via, wherein the first stressor alters an electromigration stress profile for the interconnect by altering a stress at the first area to be less tensile.
1. An integrated circuit device comprising:
a first line in a first metal layer of the integrated circuit device, wherein the first line forms at least a portion of an interconnect;
a second line in a second metal layer of the integrated circuit device;
a first via that couples the first line to the second line; and
a first stressor disposed at a first area of the interconnect, wherein the first area at least partially overlaps the first via, wherein the first stressor alters an electromigration stress profile for the interconnect by altering a stress at the first area to be less tensile;
wherein the first stressor is made of a dielectric material and is disposed on a first surface of the first line directly opposite to the first via, which is disposed at a second surface of the first line.
2. The integrated circuit device of claim 1 , wherein the first area comprises a local cathode determined based on a direction of an electric current in the interconnect.
3. The integrated circuit of claim 2 , wherein the first stressor comprises a tensile stressor that imparts a compressive stress at the first area.
4. The integrated circuit device of claim 1 , wherein the first area comprises a local anode determined based on a direction of an electric current in the interconnect.
5. The integrated circuit device of claim 4 , wherein the first stressor comprises a compressive stressor that imparts a tensile stress at the first area.
6. The integrated circuit device of claim 1 , wherein the first stressor is disposed adjacent to the first line.
7. The integrated circuit device of claim 1 , wherein the first via is connected to the first line and forms at least a portion of the interconnect.
8. The integrated circuit device of claim 1 , wherein the first stressor comprises a stress-inducing material that alters the stress at the first area.
9. The integrated circuit device of claim 1 , wherein the first stressor is wholly disposed within a first threshold distance of the first via.
10. The integrated circuit device of claim 1 further comprising a set of additional vias within a second threshold distance of the first via, wherein each via of the set of additional vias couples the first line to the second line.
11. An integrated circuit device comprising:
a first line in a first metal layer of the integrated circuit device, wherein the first line forms at least a portion of an interconnect;
a second line in a second metal layer of the integrated circuit device;
a first via that couples the first line to the second line; and
a first stressor, made of a dielectric material, disposed at a first area of the interconnect, wherein the first area at least partially overlaps the first via, wherein the first stressor is characterized as a tensile stressor and alters an electromigration stress profile for the interconnect by altering a stress at the first area to be less tensile;
a third line in the second or a third metal layer of the integrated circuit device;
a second via that connects the first line to the third line; and
a second stressor, made of a dielectric material, disposed at a second area of the interconnect, wherein the second area at least partially overlaps the second via, wherein the second stressor is characterized as a compressive stressor and is configured to alter the electromigration stress profile for the interconnect by altering a stress at the second area to be less compressive.
12. The integrated circuit device of claim 11 , wherein the first stressor is disposed on a first surface of the first line directly opposite to the first via, which is disposed at a second surface of the first line.
13. The integrated circuit device of claim 12 , wherein the second stressor is disposed on the first surface of the first line directly opposite to the second via, which is disposed at the second surface of the first line.
14. The integrated circuit device of claim 11 , wherein the first stressor is disposed adjacent to the first via.
15. The integrated circuit device of claim 14 , wherein the first stressor at least partially surrounds the first via.
16. The integrated circuit device of claim 15 further comprising a barrier layer disposed between the first via and the first line, and the first stressor is disposed where the barrier layer meets the first via and the first line.
17. The integrated circuit device of claim 11 , wherein the second stressor at least partially surrounds the second via.
18. The integrated circuit device of claim 17 further comprising a barrier layer disposed between the second via and the first line, and the second stressor is disposed where the barrier layer meets the second via and the first line.
19. The integrated circuit device of claim 11 , wherein the second stressor is disposed on a surface of the first line directly opposite to the second via, which is disposed at a surface of the first line.