Input buffer with selectable hysteresis and speed
A buffer provides a signal at an output node as a function of an input signal. First and second buffer stages have respective current conduction paths for asserting the output signal. An enabling element selectively enables the second buffer stage in response to assertion of an enabling signal in a state where the first and second buffer stages are both simultaneously enabled. The first buffer stage has hysteresis feedback paths from the output node for providing hysteresis in the buffer response. The hysteresis is smaller when the first and second buffer stages are both enabled than when only the first buffer stage is enabled. The response of the second buffer stage to the input signal, when enabled, is faster than the first buffer stage.
1. A buffer for providing a buffer output signal as a function of a first signal at a first node from an external source, the buffer comprising:
first and second buffer stages having respective current conduction paths for asserting a second signal at a second node as a function of the first signal; and
a first enabling element for selectively enabling the second buffer stage in response to assertion of a first enabling signal in a state where the first and second buffer stages are both simultaneously enabled;
wherein the first buffer stage has at least one hysteresis feedback path from the second node for providing hysteresis in the response of the second signal to the first signal; and
wherein the buffer presents a hysteresis that is smaller when the first and second buffer stages are both enabled than when the first buffer stage is enabled and the second buffer stage is disabled.
2. The buffer of claim 1 , wherein the first node is connected to an input/output (I/O) pad, and the buffer has a second enabling element for selectively enabling the first and second buffer stages in response to assertion of a second enabling signal.
3. The buffer of claim 2 , wherein the first and second enabling elements comprise switches controlled by the first and second enabling signals and connected in series with the current conduction paths of the first and second buffer stages, and wherein the first enabling element is connected in series between the current conduction path of the second buffer stage and the second enabling element.
4. The buffer of claim 1 , wherein:
the first and second buffer stages comprise first and second logic inverters respectively, and power supply rails at different voltages,
each of the inverters has first and second complementary legs connected in series in the current conduction paths between the second node and respective power supply rails, and
each of the inverters has pairs of transistors of first and second complementary conductivity types connected in series to conduct current in the first and second legs respectively, the complementary pairs of transistors being controlled by the first signal.
5. The buffer of claim 4 , wherein:
the first inverter has at least two complementary pairs of the transistors connected to conduct current in series in the legs of the first inverter, with transistors of the first and second conductivity types connected together in series in the first and second legs at first and second feedback nodes respectively, and
the hysteresis feedback path comprises first and second biasing elements for biasing the first and second feedback nodes respectively as complementary functions of the second signal.
6. The buffer of claim 4 , wherein:
the enabling element for selectively enabling the second buffer stage comprises complementary switches controlled by the first enabling signal and connected in series in the first and second legs of the second inverter,
the first node is connected to an input/output (I/O) pad, and
the buffer has further complementary switches controlled by a further enabling signal and connected in series with both the current conduction paths of the first and second buffer stages for selectively enabling the first and second buffer stages in response to assertion of the further enabling signal.
7. The buffer of claim 1 , wherein the hysteresis feedback path of the first buffer stage provides hysteresis of the buffer when both the second buffer stage and the first buffer stage are enabled.
8. The buffer of claim 1 , further comprising an inverter connected to the second node that provides the buffer output signal as a function of the second signal.
9. A buffer for providing a buffer output signal as a function of a first signal at a first node from an external source, the buffer comprising:
first and second buffer stages having respective current conduction paths for asserting a second signal at a second node as a function of the first signal; and
an enabling element for selectively enabling the second buffer stage in response to assertion of an enabling signal in a state where the first and second buffer stages are both simultaneously enabled;
wherein the first buffer stage has at least one hysteresis feedback path from the second node for providing hysteresis in the response of the second signal to the first signal; and
wherein the response of the second buffer stage to the first signal, when enabled, is faster than the response of the first buffer stage.
10. The buffer of claim 9 , wherein the first node is connected to an input/output (I/O) pad, and the buffer has a second enabling element for selectively enabling the first and second buffer stages in response to assertion of a second enabling signal.
11. The buffer of claim 9 , wherein the first and second buffer stages comprise pairs of transistors of first and second complementary conductivity types, and wherein the transistors of the second buffer stage of each conductivity type are larger than the transistors of the first buffer stage of the same conductivity type.
12. A buffer for providing a buffer output signal as a function of a first signal at a first node from an external source, the buffer comprising:
first and second buffer stages having respective current conduction paths for asserting a second signal at a second node as a function of the first signal; and
an enabling element for selectively enabling the second buffer stage in response to assertion of an enabling signal in a state where the first and second buffer stages are both simultaneously enabled;
wherein the first buffer stage has at least one hysteresis feedback path from the second node for providing hysteresis in the response of the second signal to the first signal;
wherein the buffer presents a hysteresis that is smaller when the first and second buffer stages are both enabled than when the first buffer stage is enabled and the second buffer stage is disabled; and
wherein the response of the second buffer stage to the first signal, when enabled, is faster than the response of the first buffer stage.
13. The buffer of claim 12 , wherein the first node is connected to an input/output (I/O) pad, and the buffer has a second enabling element for selectively enabling the first and second buffer stages in response to assertion of a second enabling signal.
14. The buffer of claim 13 , wherein:
the enabling elements comprise switches controlled by the enabling signals and connected in series with the current conduction paths of the first and second buffer stages, and
the enabling element for selectively enabling the second buffer stage is connected in series between the current conduction path of the second buffer stage and the second enabling element.
15. The buffer of claim 12 , wherein:
the first and second buffer stages comprise first and second logic inverters respectively, and power supply rails at different voltages,
each of the inverters has first and second complementary legs connected in series in the current conduction paths between the second node and respective power supply rails, and
each of the inverters has pairs of transistors of first and second complementary conductivity types connected in series in the first and second legs respectively to conduct current, the complementary pairs of transistors being controlled by the first signal.
16. The buffer of claim 15 , wherein:
the first inverter has at least two complementary pairs of the transistors connected to conduct current in series in the legs of the first inverter, with transistors of the first and second conductivity types connected together in series in the first and second legs at first and second feedback nodes respectively, and
the hysteresis feedback path comprises first and second biasing elements for biasing the first and second feedback nodes respectively as complementary functions of the second signal.
17. The buffer of claim 15 , wherein:
the enabling element for selectively enabling the second buffer stage comprises first complementary switches controlled by the enabling signal and connected in series in the first and second legs of the second inverter, wherein the first node is connected to an input/output (I/O) pad, and
the buffer has second complementary switches controlled by a second enabling signal and connected in series with both the current conduction paths of the first and second buffer stages for selectively enabling the first and second buffer stages in response to assertion of the second enabling signal.
18. The buffer of claim 12 , wherein the first and second buffer stages comprise pairs first and second complementary conductivity type transistors, wherein the transistors of the second buffer stage of each conductivity type are larger than the transistors of the first buffer stage of the same conductivity type.
19. The buffer of claim 12 , wherein the hysteresis feedback path of the first buffer stage provides hysteresis of the buffer when both the second buffer stage and the first buffer stage are enabled.
20. The buffer of claim 12 , further comprising an inverter connected to the second node that provides the buffer output signal as a function of the second signal.