Delay compensated continuous time sigma delta analog-to-digital converter
View Patent ↗A continuous time sigma delta analog to digital converter is provided. The continuous time sigma delta analog to digital converter may include, but is not limited to, an analog to digital converter having a feedback loop, and a feedback loop controller coupled to the analog to digital converter, the feedback loop controller configured to adjust delay in the feedback loop by controlling a variable delay component in the feedback loop.
1. A continuous time sigma delta modulator, comprising:
an analog to digital converter including a feedback loop, wherein the feedback loop comprises a delay element; and
a delay controller configured to be coupled to the delay element, the delay controller configured to adjust a delay in the feedback loop by controlling the delay element based upon a delay in the feedback loop,
wherein the delay element comprises a plurality of controlled and non-controlled delay elements, and a first set of the plurality of delay elements are configured to remove a fixed amount of delay from the feedback loop and a second set of the plurality of delay elements are coupled to the delay controller and are configured to remove a variable amount of delay from the feedback loop based upon a control signal of the delay controller.
2. The continuous time sigma delta modulator of claim 1 , wherein the delay controller is configured to remove a delay in the feedback loop when optimizing the delay.
3. A continuous time sigma delta modulator, comprising:
an analog to digital converter including a feedback loop, wherein the feedback loop comprises a delay element; and
a delay controller configured to be coupled to the delay element, the delay controller configured to adjust a delay in the feedback loop by controlling the delay element based upon a delay in the feedback loop,
wherein the delay controller includes a counter.
4. A continuous time sigma delta modulator, comprising:
an analog to digital converter including a feedback loop, wherein the feedback loop comprises a delay element; and
a delay controller configured to be coupled to the delay element, the delay controller configured to adjust a delay in the feedback loop by controlling the delay element based upon a delay in the feedback loop,
wherein the delay controller includes a charge pump.
5. A continuous time sigma delta modulator, comprising:
an analog to digital converter including a feedback loop, wherein the feedback loop comprises a delay element;
a delay controller configured to be coupled to the delay element, the delay controller configured to adjust a delay in the feedback loop by controlling the delay element based upon a delay in the feedback loop;
a delay locked loop configured to be coupled to the analog to digital converter and configured to output a signal indicating the phase of a received analog input signal; and
a phase detector configured to be coupled to the feedback loop, the delay controller and the delay locked loop, wherein the phase detector is configured to compare a determined phase of the feedback loop signal with the phase of the received analog input signal, and to transmit an indication of the difference between the phase of the feedback loop signal with the phase of the received analog input signal to the delay controller.
6. The continuous time sigma delta modulator of claim 5 , wherein the delay controller controls the delay element based upon the indication of the difference between the phase of the feedback loop signal with the signal indicating the phase of the received analog input signal to the delay controller.
7. A continuous time sigma delta modulator, comprising:
an analog to digital converter including a feedback loop, wherein the feedback loop comprises a delay element;
a delay controller configured to be coupled to the delay element, the delay controller configured to adjust a delay in the feedback loop by controlling the delay element based upon a delay in the feedback loop; and
a memory, wherein the delay controller is further configured to control the amount of delay removed from the feedback loop by the delay element based upon a value in the memory.
8. A continuous time sigma delta modulator, comprising:
an analog to digital converter including a feedback loop, wherein the feedback loop comprises a delay element; and
a delay controller configured to be coupled to the delay element, the delay controller configured to adjust a delay in the feedback loop by controlling the delay element based upon a delay in the feedback loop,
wherein the feedback loop comprises the delay element coupled to the output of the analog to digital converter and a digital to analog converter coupled between an input of the analog to digital converter and the delay element.
9. The continuous time sigma delta modulator of claim 8 , wherein the digital to analog converter is a non-return-to-zero digital to analog converter.
10. An analog to digital converter, comprising:
a feedback loop, comprising:
a delay element coupled to an output of the analog to digital converter; and
a digital to analog converter coupled between an input of the analog to digital converter and the delay element,
wherein the delay element is configured to optimize a delay in the feedback loop; and
a memory communicatively coupled to the delay element, the memory being configured to store an indication of an amount of delay to provide to the feedback loop, wherein the delay element is programmable to adjust the delay in the feedback loop based upon the indication of the amount of delay to be provided to feedback loop.
11. The analog to digital converter of claim 10 , wherein the delay element comprises a plurality of inverters.
12. An analog to digital converter, comprising:
a feedback loop, comprising:
a delay element coupled to an output of the analog to digital converter; and
a digital to analog converter coupled between an input of the analog to digital converter and the delay element,
wherein the delay element is configured to optimize a delay in the feedback loop,
wherein the delay element comprises a plurality of inverters and a first set of the plurality of inverters are configured to reduce a fixed amount of delay from the feedback loop and a second set of the plurality of inverters are configured to provide a variable amount of delay from the feedback loop.
13. The analog to digital converter of claim 10 , wherein the analog to digital converter is a continuous time sigma delta analog to digital converter.
14. An analog to digital converter, comprising:
a feedback loop, comprising:
a delay element coupled to an output of the analog to digital converter; and
a digital to analog converter coupled between an input of the analog to digital converter and the delay element,
wherein the delay element is configured to optimize a delay in the feedback loop,
wherein the digital to analog converter is a non-return-to-zero digital to analog converter.
15. An analog to digital converter, comprising:
a feedback loop, comprising:
a delay element coupled to an output of the analog to digital converter; and
a digital to analog converter coupled between an input of the analog to digital converter and the delay element,
wherein the delay element is configured to optimize a delay in the feedback loop; and
a delay controller communicatively coupled to the delay element, wherein the delay controller is configured to communicate a voltage corresponding to an amount of delay to be removed from the feedback loop to the delay element.
16. The analog to digital converter of claim 15 , further comprising:
a delay locked loop coupled to the analog to digital converter and configured to output a signal indicating the phase of a received analog input signal; and
a phase detector communicatively coupled to the digital to analog converter, the delay controller, and the delay locked loop, wherein the phase detector is configured to compare a determined phase of the digital to analog converter signal with the phase of the received analog input signal, and to transmit an indication of the difference between the phase of the digital to analog converter signal with the phase of the received analog input signal to the delay controller.
17. The analog to digital converter of claim 16 , further comprising a memory communicatively coupled to the delay controller and the delay element, wherein the delay controller is configured to store the indication of the difference between the phase of the digital to analog converter signal with the phase of the received analog input signal in the memory, and the delay element is configured to reduce the delay in the feedback loop based upon the indication of the difference between the phase of the digital to analog converter signal with the phase of the received analog input signal stored in the memory.