IP Library Granted Patent US 9,171,834
Granted Patent B2
US 9,171,834 · App. 13/690,046 · Granted Oct 27, 2015

Over voltage protection for a thin oxide load circuit

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Quick Facts
Patent No.
US 9,171,834
App. No.
13/690,046
Granted
Oct 27, 2015
Kind
B2
Abstract

An IC includes: a substrate having a thick oxide portion and a thin oxide portion; a load circuit disposed on the thin oxide portion and coupled between a supply node and a virtual supply node; and a current source circuit and protection circuit disposed on the substrate. The current source circuit has an output coupled to the virtual supply node and is operable to provide a voltage at the virtual supply node. The protection circuit includes a sensing portion and a protection portion. The sensing portion is coupled to the virtual supply node and is operable to detect the voltage at the virtual supply node. The protection portion is coupled to the sensing portion and is operable, in response to the sensed voltage, to prevent a difference in voltage between the voltage at the virtual supply node and a second voltage at the supply node from exceeding a maximum voltage.

Claims (32)

1. An integrated circuit that provides over voltage protection for a thin oxide load circuit, the integrated circuit comprising:

a substrate having a thick oxide portion and a thin oxide portion;

a load circuit disposed on the thin oxide portion, wherein the load circuit has a first end that is coupled to a first supply node and a second end that is directly connected to a virtual supply node;

a current source circuit disposed on the substrate, the current source circuit having an input coupled to a control signal node and an output directly connected to the virtual supply node, wherein the current source circuit is operable to provide a voltage at the virtual supply node, which is based on a control signal coupled to the control signal node;

a protection circuit disposed on the substrate and disconnected from the control signal node of the current source circuit, the protection circuit comprising a sensing portion coupled to a protection portion, wherein the sensing portion is directly connected to the virtual supply node and is operable to sense the voltage at the virtual supply node and, when the sensed voltage meets an intrinsic or extrinsic reference voltage value, to activate the protection portion, which is external to the current source circuit, wherein the protection circuit is coupled to the sensing portion and is operable in response to feedback from the sensing portion of the sensed voltage, to clamp a difference in voltage between the voltage at the virtual supply node and a second voltage at the first supply node to a first maximum voltage value that is established by the second voltage at the first supply node and the control signal, the magnitude of which is set by a source external to the protection circuit.

2. The integrated circuit of claim 1 , wherein the load circuit comprises a ring oscillator that includes a chain of an odd number of inverters, wherein each inverter has a first terminal connected to the first supply node and a second terminal connected to the virtual supply node.

3. The integrated circuit of claim 2 , wherein the ring oscillator comprises a single-ended oscillator or a differential oscillator.

4. The integrated circuit of claim 2 , wherein the ring oscillator comprises three inverters.

5. The integrated circuit of claim 1 , wherein the protection circuit is disposed on the thin oxide portion or the thick oxide portion of the substrate.

6. The integrated circuit of claim 1 , wherein the protection circuit comprises a diode having a first terminal coupled to the virtual supply node and a second terminal coupled to the first supply node or to a maximum voltage node that is configured to receive a second maximum voltage value.

7. The integrated circuit of claim 1 , wherein the protection circuit comprises a diode-connected transistor comprising a first terminal connected to the virtual supply node and a second and third terminal coupled to the first supply node or to a maximum voltage node that is configured to receive a second maximum voltage value.

8. The integrated circuit of claim 7 , wherein the diode-connected transistor comprises an N-channel Metal Oxide Semiconductor transistor or a P-channel Metal Oxide Semiconductor transistor.

9. The integrated circuit of claim 7 , wherein the second terminal comprises a gate terminal, and the second and third terminal are connected together and connected to the first supply node or to the maximum voltage node.

10. The integrated circuit of claim 7 , wherein the second terminal comprises a gate terminal, and wherein the integrated circuit further comprises a Complementary Metal-Oxide Semiconductor (CMOS) transmission gate connected between the gate terminal and the first supply node or the maximum voltage node to control conductivity of the diode-connected transistor using first and second enabling voltages.

11. The integrated circuit of claim 1 , wherein the sensing portion of the protection circuit comprises a comparator having a first input terminal connected to the virtual supply node, a second input terminal connected to a voltage reference node that is configured to receive a reference voltage, and an output terminal, wherein the comparator is configured for operating in two states to switch an operation of a device having an input connected to the output terminal.

12. The integrated circuit of claim 11 , wherein the protection portion of the protection circuit comprises a transistor having a gate terminal connected to the output terminal of the comparator, a second terminal connected to the first supply node and a third terminal connected to the virtual supply node.

13. The integrated circuit of claim 11 further comprising a resistor connected between the supply node and a supply input node, wherein the protection portion of the protection circuit comprises a transistor having a gate terminal connected to the output terminal of the comparator, a second terminal connected to the first supply node and a third terminal connected to a second supply node.

14. The integrated circuit of claim 11 , wherein the protection portion of the protection circuit comprises a first inverter having an input terminal connected to the output terminal of the comparator and an output terminal connected to the control signal node and a second inverter having an input terminal connected to the output terminal of the first inverter, wherein the second inverter is operative to provide an alert signal.

15. The integrated circuit of claim 11 , wherein the protection portion of the protection circuit comprises:

a first inverter having an input terminal connected to the output terminal of the comparator and an output terminal;

a Complementary Metal-Oxide Semiconductor (CMOS) transmission gate connected between the virtual supply node and a maximum voltage node that is configured to receive a second maximum voltage value, the CMOS transmission gate comprising a first gate terminal connected to the output terminal of the comparator and a second gate terminal connected to the output terminal of the first inverter; and

a second inverter having an input terminal connected to the output terminal of comparator, wherein the second inverter is operative to provide an alert signal.

16. The integrated circuit of claim 1 , wherein the current source circuit comprises an N-channel Metal Oxide Semiconductor transistor or a P-channel Metal Oxide Semiconductor transistor having a gate terminal connected to the control signal node, a second terminal connected to the virtual supply node and a third terminal connected to a second supply node.

17. A method of fabricating an integrated circuit on a substrate having a thick oxide portion and a thin oxide portion, the method comprising:

forming a load circuit on the thin oxide portion of the substrate, wherein the load circuit has a first end that is coupled to a first supply node and a second end that is directly connected to a virtual supply node;

forming a current source circuit on the current source circuit having an input coupled to a control signal node and an output directly connected to the virtual supply node, wherein the current source circuit is operable to provide a voltage at the virtual supply node, which is based on a control signal coupled to the control signal node;

forming a protection circuit on the substrate wherein the protection circuit is disconnected from the control signal node of the current source circuit, the protection circuit comprising a sensing portion coupled to a protection portion, wherein the sensing portion is directly connected to the virtual supply node and is operable to sense the voltage at the virtual supply node and, when the sensed voltage meets an intrinsic or extrinsic reference voltage value, to activate the protection portion, which is external to the current source circuit, wherein the protection circuit is coupled to the sensing portion and is operable, in response to feedback from the sensing portion of the sensed voltage, to clamp a difference in voltage between the voltage at the virtual supply node and a second voltage at the first supply node to a first maximum voltage value that is established by the second voltage at the first supply node and the control signal, the magnitude of which is set by a source external to the protection circuit.

18. The method of claim 17 , wherein the integrated circuit is fabricated using a Complementary Metal-Oxide Semiconductor process.

19. The method of claim 18 , wherein:

forming the current source circuit on the substrate comprises forming on the thick oxide portion of the substrate an N-channel Metal Oxide Semiconductor transistor or a P-channel Metal Oxide Semiconductor transistor having a gate terminal connected to the control signal node, a second terminal connected to the virtual supply node and a third terminal connected to a second supply node;

forming the protection circuit on the substrate comprises forming the protection circuit on the thick oxide portion of the substrate.

20. The method of claim 17 , wherein forming the load circuit on the thin oxide portion of the substrate comprises forming a ring oscillator that includes a chain of an odd number of inverters, wherein each inverter has a first terminal connected to the first supply node and a second terminal connected to the virtual supply node.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
PATENT RELEASE Recorded Jan 14, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037494/0312 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0671 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0685 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2012
From: TANG, XINGHAI; SANCHEZ, HECTOR
To: FREESCALE SEMICONDUCTOR, INC.
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