IP Library Granted Patent US 8,927,417
Granted Patent B2
US 8,927,417 · App. 13/718,081 · Granted Jan 6, 2015

Semiconductor package signal routing using conductive vias

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Quick Facts
Patent No.
US 8,927,417
App. No.
13/718,081
Granted
Jan 6, 2015
Kind
B2
Abstract

A mechanism is provided by which signal travel distance within and between semiconductor device packages is reduced and substrate size and complexity can be reduced. This capacity is provided by virtue of a conductive via that intersects a wire bond molded within a package substrate. The via provides a direct electrical connection between an external signal transmitter or receiver and the points connected by the wire bond, and thereby avoiding the need for the signal to transit built up interconnects in the semiconductor device package. Conductive vias can provide connectivity through or to a package substrate, and can be through vias or blind vias. The conductive via is formed by either mechanical or laser drilling, and is filled using standard fill techniques, and is therefore readily incorporated into a package production flow.

Claims (33)

1. A method for packaging an electronic device assembly, the method comprising:

electrically coupling an electronic device to one or more signal pads, wherein said electrically coupling is performed using corresponding wire bonds;

forming an encapsulant over and around sides of the electronic device and over and around the wire bonds and signal pads to provide an encapsulated electronic device assembly, wherein the encapsulated electronic device assembly comprises a first and second opposing major surfaces;

drilling a hole from one of the first or second major surface toward the opposing major surface, wherein the hole severs a wire bond electrically coupling the electronic device to a signal pad of the one or more signal pads; and

filling the hole with a conductive material to form a conductive via having a contact surface at or near the major surface from which the hole is drilled, wherein

the conductive via is in electrical contact with severed ends of the severed wire bond, and

the conductive via electrically couples the contact surface with the severed ends of the severed wire bond.

2. The method of claim 1 further comprising:

providing a package substrate comprising the one or more signal pads; and

placing the electronic device in an area of the package substrate for the electronic device assembly, wherein

said forming the encapsulant further comprises forming the encapsulant over the package substrate in the area for the electronic device assembly, and

the first major surface of the encapsulated device assembly comprises the package substrate.

3. The method of claim 2 wherein said drilling the hole from one of the first or second major surface comprises drilling the hole through the package substrate from the first major surface.

4. The method of claim 3 further comprising:

forming a first solder ball on the first major surface of the electronic device assembly subsequent to said forming the encapsulant, wherein the first solder ball is coupled to a signal contact on the package substrate; and

forming a second solder ball on the contact surface of the conductive via.

5. The method of claim 2 wherein said drilling the hole from one of the first or second major surface comprises drilling the hole from the second major surface to the package substrate but not through the package substrate.

6. The method of claim 5 wherein said filling the hole with a conductive material further forms the conductive via electrically coupled with a signal contact on the package substrate.

7. The method of claim 1 , wherein

said drilling the hole from one of the first or second major surface toward the opposing major surface further comprises drilling the hole through the opposing major surface, and

said filling the hole with a conductive material forms a through via further having a second contact surface at or near the major surface opposing the major surface from which the hole is drilled.

8. The method of claim 1 further comprising:

placing a second electronic device assembly on one of the first or second major surface of the encapsulated electronic device assembly from which the hole is drilled; and

forming an electrical connection between a signal contact on the second electronic device assembly and the contact surface of the conductive via of the encapsulated electronic device assembly.

9. The method of claim 8 wherein said forming the electrical connection comprises using a solder ball between the signal contact on the second electronic device assembly and the contact surface.

10. The method of claim 8 wherein said forming the electrical connection comprises performing a solder reflow.

11. The method of claim 1 wherein the wire bond comprises one or more of gold, copper, aluminum, and palladium.

12. The method of claim 1 wherein the conductive material forming the conductive via comprises a solder paste.

13. The method of claim 1 further comprising:

providing a lead frame comprising the one or more signal pads and a die pad; and

placing the electronic device on the die pad, wherein

said forming the encapsulant further comprises forming the encapsulant over the lead frame and around sides of the lead frame, and

the first major surface of the encapsulated device assembly comprises the lead frame.

Assignments (23)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
PATENT RELEASE Recorded Jan 14, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037494/0312 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0671 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0685 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 030258/0540 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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CORRECTIVE ASSIGNMENT TO CORRECT THE TITLE PREVIOUSLY RECORDED ON REEL 029489 FRAME 0545. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 19, 2013
From: YAP, WENG FOONG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029834/0939 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2012
From: YAP, WENG FOONG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029489/0545 →