Patent Assignment
Reel/Frame 040632/0001
CHANGE OF NAME
Recorded: 2016-11-08
Received: 2016-11-08
Pages: 34
Assignor
FREESCALE SEMICONDUCTOR, INC.
Executed: 2016-11-07
Assignee
NXP USA, INC.
6501 WILLIAM CANNON DRIVE WEST, AUSTIN, TX, 78735, UNITED STATES
Covered Applications
(100)
LOW-VOLTAGE DIFFERENTIAL SIGNALING (DIFFERENTIAL SIGNALING) DRIVER CIRCUIT AND METHOD OF ENABLING AND DISABLING A DIFFERENTIAL SIGNALING DRIVER CIRCUIT
App. No. 15/035,544
→
GLITCH-FREE CLOCK SWITCHING CIRCUIT USING MULLER C-ELEMENTS
App. No. 15/139,337
→
TEXT SELECTION USING A TOUCH SENSITIVE SCREEN OF A HANDHELD MOBILE COMMUNICATION DEVICE
App. No. 15/056,861
→
VARIABLE FREQUENCY RELAXATION OSCILLATOR
App. No. 14/989,626
→
EXPOSED PAD INTEGRATED CIRCUIT PACKAGE WITH MOLD LOCK
App. No. 14/929,381
→
LEAD FRAME WITH DEFLECTING TIE BAR FOR IC PACKAGE
App. No. 14/887,304
→
A FOOD PREPARATION CAPSULE
App. No. 14/780,312
→
SENSING FIELD EFFECT TRANSISTOR DEVICES AND METHOD OF THEIR MANUFACTURE
App. No. 14/854,265
→
INTEGRATED CIRCUIT PACKAGE HAVING SIDE AND BOTTOM CONTACT PADS
App. No. 14/850,958
→
IC PACKAGE HAVING NON-HORIZONTAL DIE PAD AND LEAD FRAME THEREFOR
App. No. 14/850,966
→
LOW-POWER OPEN-CIRCUIT DETECTION SYSTEM
App. No. 14/843,997
→
SEMICONDUCTOR DEVICE WITH HEAT-DISSIPATING LEAD FRAME
App. No. 14/843,967
→
MICROELECTRONIC PACKAGES HAVING RADIO FREQUENCY STAND-OFF LAYERS
App. No. 14/825,870
→
MICROELECTRONIC PACKAGES HAVING STACKED ACCELEROMETER AND MAGNETOMETER DIE AND METHODS FOR THE PRODUCTION THEREOF
App. No. 14/806,481
→
NON-VOLATILE DYNAMIC RANDOM ACCESS MEMORY (NVDRAM)
App. No. 14/788,285
→
SYNCHRONOUS COMMUNICATION BETWEEN SYSTEM IN PACKAGE (SIP) DEVICES
App. No. 14/788,363
→
METHOD FOR TESTING ANALOG-TO-DIGITAL CONVERTER AND SYSTEM THEREFOR
App. No. 14/751,804
→
RAMP VOLTAGE GENERATOR AND METHOD FOR TESTING AN ANALOG-TO-DIGITAL CONVERTER
App. No. 14/745,641
→
METHOD FOR TESTING DIFFERENTIAL ANALOG-TO-DIGITAL CONVERTER AND SYSTEM THEREFOR
App. No. 14/745,653
→
ELECTRIC MOTOR THERMAL MANAGEMENT
App. No. 14/745,456
→
QUAD FLAT NON-LEADED SEMICONDUCTOR PACKAGE WITH WETTABLE FLANK
App. No. 14/743,986
→
VOLTAGE LEVEL SHIFTER FOR HIGH VOLTAGE APPLICATIONS
App. No. 14/743,828
→
NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM)
App. No. 14/741,674
→
TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) WITH MAGNETIC TUNNEL JUNCTION (MTJ) DEVICES
App. No. 14/734,742
→
METHOD AND APPARATUS FOR ASSEMBLING A SEMICONDUCTOR PACKAGE
App. No. 14/722,810
→
CLOCK SIGNAL ALIGNMENT FOR SYSTEM-IN-PACKAGE (SIP) DEVICES
App. No. 14/719,549
→
STACKED MICROELECTRONIC PACKAGES HAVING SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF
App. No. 14/706,359
→
RESURF SEMICONDUCTOR DEVICE CHARGE BALANCING
App. No. 14/697,963
→
SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURE
App. No. 14/696,917
→
ANALOG-TO-DIGITAL CONVERTER WITH CONTROLLED ERROR CALIBRATION
App. No. 14/696,482
→
FSK DEMODULATOR
App. No. 14/694,927
→
BOND WIRE FEED SYSTEM AND METHOD THEREFOR
App. No. 14/693,881
→
POWER MANAGEMENT SYSTEM FOR INTEGRATED CIRCUITS
App. No. 14/693,884
→
INTEGRATED CIRCUIT WITH SEWN INTERCONNECTS
App. No. 14/692,747
→
EMBEDDED DIE BALL GRID ARRAY PACKAGE
App. No. 14/688,976
→
SEMICONDUCTOR DEVICE AND LEAD FRAME HAVING VERTICAL CONNECTION BARS
App. No. 14/677,964
→
PHASE LOCKED LOOP HAVING FRACTIONAL VCO MODULATION
App. No. 14/631,305
→
INTEGRATED CIRCUIT CARRIER COATING
App. No. 14/626,242
→
PROGRAMMABLE BUFFER SYSTEM
App. No. 14/612,774
→
SYSTEMS AND METHODS FOR CALIBRATING A DUAL PORT PHASE LOCKED LOOP
App. No. 14/604,428
→
AUTOMATIC RECEIVED GAIN CONTROL
App. No. 14/603,443
→
DC OFFSET TRACKING OF WIRELESS RECEIVERS
App. No. 14/604,291
→
MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICES WITH CONTROL CIRCUITS AND METHODS OF FABRICATION
App. No. 14/593,582
→
INTERPOSER WITH OVERMOLDED VIAS
App. No. 14/591,934
→
METHOD FOR FORMING MULTILAYER DEVICE HAVING SOLDER FILLED VIA CONNECTION
App. No. 14/591,933
→
SYSTEMS AND METHODS FOR OPERATING RADIO TRANSCEIVERS
App. No. 14/582,186
→
INTEGRATED CIRCUIT WTH LOW POWER SCAN FLIP-FLOP
App. No. 14/580,237
→
DIE-TO-DIE INDUCTIVE COMMUNICATION DEVICES AND METHODS
App. No. 14/573,674
→
REAL-SPACE CHARGE-TRANSFER DEVICE AND METHOD THEREOF
App. No. 14/573,891
→
Thin Beam Deposited Fuse
App. No. 14/570,179
→
SCAN TESTING WITH STAGGERED CLOCKS
App. No. 14/566,823
→
FLOATING MOLD TOOL FOR SEMICONDCUTOR PACKAGING
App. No. 14/562,770
→
Thermally Enhanced Package with Lid Heat Spreader
App. No. 14/560,678
→
PACKAGED SEMICONDUCTOR SENSOR DEVICE WITH LID
App. No. 14/559,921
→
COPPER BALL BOND FEATURES AND STRUCTURE
App. No. 14/557,769
→
RELAXATION OSCILLATOR
App. No. 14/556,220
→
PACKAGED INTEGRATED CIRCUIT DEVICE HAVING BENT LEADS
App. No. 14/554,065
→
SEMICONDUCTOR DEVICE WITH TUBE BASED HEAT SPREADER
App. No. 14/555,565
→
TURBO DECODERS WITH EXTRINSIC ADDRESSING AND ASSOCIATED METHODS
App. No. 14/555,373
→
TURBO DECODER WITH A LOW-POWER INPUT FORMAT AND ASSOCIATED METHOD
App. No. 14/555,309
→
CLEANING MECHANISM FOR SEMICONDUCTOR SINGULATION SAWS
App. No. 14/555,562
→
PROTECTIVE PACKAGING FOR INTEGRATED CIRCUIT DEVICE
App. No. 14/554,058
→
DIE EDGE SEAL EMPLOYING LOW-K DIELECTRIC MATERIAL
App. No. 14/555,558
→
SEMICONDUCTOR DEVICE ASSEMBLED USING TWO LEAD FRAMES
App. No. 14/554,064
→
WIRE BONDING METHOD EMPLOYING TWO SCRUB SETTINGS
App. No. 14/552,472
→
SEMICONDUCTOR DEVICE HAVING LEAD FRAME WITH NOTCHED INNER LEADS
App. No. 14/551,075
→
SEMICONDUCTOR DIE PACKAGE WITH PRE-MOLDED DIE
App. No. 14/551,069
→
SEMICONDUCTOR DEVICE GRID ARRAY PACKAGE
App. No. 14/551,070
→
TELECONFERENCING ENVIRONMENT HAVING AUDITORY AND VISUAL CUES
App. No. 14/543,031
→
THOUGH-SUBSTRATE VIAS (TSVS) AND METHOD THEREFOR
App. No. 14/539,421
→
SIMULATION SYSTEM AND METHOD FOR TESTING A SIMULATION OF A DEVICE AGAINST ONE OR MORE VIOLATION RULES
App. No. 14/398,901
→
COATED BONDING WIRE AND METHODS FOR BONDING USING SAME
App. No. 14/529,744
→
ANTENNA-DIVERSITY RECEIVER AND METHOD OF OPERATING AN ANTENNA-DIVERSITY RECEIVER AND A TRANSMITTER IN A FREQUENCY-HOPPING COMMUNICATION SYSTEM
App. No. 14/528,567
→
CAVITY-TYPE SEMICONDUCTOR PACKAGE AND METHOD OF PACKAGING SAME
App. No. 14/527,421
→
COATING LAYER FOR A CONDUCTIVE STRUCTURE
App. No. 14/525,855
→
SYSTEM FOR REDUCING POWER CONSUMPTION OF INTEGRATED CIRCUIT
App. No. 14/523,958
→
SEMICONDUCTOR DEVICE WITH WEBBING BETWEEN LEADS
App. No. 14/517,934
→
VOLTAGE LEVEL SHIFTER MODULE
App. No. 14/516,656
→
SEMICONDUCTOR DEVICE HAVING A NANOTUBE LAYER AND METHOD FOR FORMING
App. No. 14/513,980
→
FAN-OUT WAFER LEVEL PACKAGES CONTAINING EMBEDDED GROUND PLANE INTERCONNECT STRUCTURES AND METHODS FOR THE FABRICATION THEREOF
App. No. 14/500,698
→
SUBSTRATE FOR ALTERNATIVE SEMICONDUCTOR DIE CONFIGURATIONS
App. No. 14/499,266
→
SEMICONDUCTOR DEVICE AND METHOD OF ASSEMBLING SAME
App. No. 14/499,240
→
SUBSTRATE WITH ELECTRICALLY ISOLATED BOND PADS
App. No. 14/499,264
→
INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIRCUIT MATERIAL AND CHIP LEADS OF THE INTEGRATED CIRCUIT, AND FOR OPTIMIZING PERFORMANCE OF DEVICES OF THE INTEGRATED CIRCUIT
App. No. 14/496,870
→
METHOD OF VALIDATING TIMING ISSUES IN GATE-LEVEL SIMULATION
App. No. 14/488,313
→
SEMICONDUCTOR DEVICE WITH PLATED THROUGH HOLES
App. No. 14/477,885
→
NON-HOMOGENEOUS MOLDING OF PACKAGED SEMICONDUCTOR DEVICES
App. No. 14/474,291
→
SEMICONDUCTOR DEVICE PACKAGE WITH ORGANIC INTERPOSER
App. No. 14/474,294
→
SWITCHING SCHEME TO EXTEND MAXIMUM INPUT VOLTAGE RANGE OF A DC-TO-DC VOLTAGE CONVERTER
App. No. 14/472,903
→
MICROELECTRONIC PACKAGES HAVING TEXTURIZED SOLDER PADS AND METHODS FOR THE FABRICATION THEREOF
App. No. 14/470,679
→
METHOD AND APPARATUS FOR PERFORMING INTEGRATED CIRCUIT LAYOUT VERIFICATION
App. No. 14/380,384
→
LEAD FRAME BASED SEMICONDUCTOR DEVICE WITH ROUTING SUBSTRATE
App. No. 14/462,565
→
SEMICONDUCTOR DEVICE WITH HEAT SPREADER
App. No. 14/462,567
→
COMMON PIN FOR MULTI-DIE SEMICONDUCTOR PACKAGE
App. No. 14/459,337
→
SEMICONDUCTOR DEVICE PACKAGE WITH CAP ELEMENT
App. No. 14/459,331
→
SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURE
App. No. 14/453,902
→
DUAL HIGH-K OXIDES WITH SIGE CHANNEL
App. No. 14/452,736
→
METHODS FOR REMOVING ADHESIVE LAYERS FROM SEMICONDUCTOR WAFERS
App. No. 14/448,186
→
SYSTEMS AND METHODS FOR TEST CIRCUITRY FOR INSULATED-GATE BIPOLAR TRANSISTORS
App. No. 14/341,286
→
Address Fault Detection Circuit
App. No. 14/339,049
→