Systems and methods for calibrating a dual port phase locked loop
View Patent ↗The present disclosure provides for a phase-locked loop (PLL) that includes a high-port calibration control module configured to calibrate an input modulation value of a voltage-controlled oscillator (VCO) to a first modulation value that results in an output signal of the VCO having a positive frequency change from an initial output frequency, and capture a positive frequency value of the output signal after a first accumulation time period. The high-port calibration control module is also configured to calibrate the input modulation value of the VCO to a second modulation value that results in the output signal having a negative frequency change from the initial output frequency, capture a negative frequency value of the output signal after a second accumulation time period, and calculate a calibration scale factor based on a difference between the positive and negative frequency values.
1. A phase-locked loop (PLL) comprising:
a voltage-controlled oscillator (VCO) configured to generate an output signal having variable frequency;
a high-port modulator coupled to the VCO, the high-port modulator configured to inject a modulation signal into the VCO, based on an input modulation value; and
a high-port calibration control module configured to
calibrate the input modulation value to a first modulation value that results in the output signal having a positive frequency change from an initial output frequency,
capture a positive frequency value of the output signal after a first accumulation time period,
calibrate the input modulation value to a second modulation value that results in the output signal having a negative frequency change from the initial output frequency,
capture a negative frequency value of the output signal after a second accumulation time period,
calculate a calibration scale factor based on a difference between the positive and negative frequency values,
calculate a plurality of frequency scale factors associated with the calibration scale factor, wherein
each of the plurality of frequency scale factors corresponds to one of a plurality of reference frequencies, and
each of the plurality of reference frequencies are configured to be utilized as an input control frequency to the VCO, and
store the plurality of frequency scale factors and the calibration scale factor in a lookup table.
2. The PLL of claim 1 , wherein
the high-port modulator includes a plurality of modulation steps,
each modulation step corresponds to a frequency deviation in VCO output, and
the calibration scale factor is configured to map one or more modulation steps to an accurate frequency deviation in VCO output.
3. The PLL of claim 1 , wherein the calibration scale factor is configured to calibrate the input modulation value to a calibrated modulation value that results in the output signal of the VCO having an accurate frequency deviation around a target frequency to which the PLL is locked.
4. The PLL of claim 3 , wherein
the PLL further comprises a sigma-delta modulator configured to receive a low-port modulation value that results in a low-port modulation frequency response at VCO output, and
the calibrated modulation value results in a high-port modulation frequency response at VCO output that is complimentary to the low-port modulation frequency response at VCO output.
5. The PLL of claim 1 , wherein the high-port calibration control module is configured to calculate the calibration scale factor by being further configured to:
calculate a change in modulation value equal to a difference between the first and second modulation values;
calculate a change in output frequency equal to a difference between the positive and negative frequency values;
calculate calibration resolution equal to the change in output frequency divided by the change in modulation value; and
calculate the calibration scale factor equal to a low-port modulation resolution divided by the calibration resolution,
wherein the low-port modulation resolution is equal to a reference frequency divided by base 2 raised to a number of modulation steps available in a low-port modulator.
6. The PLL of claim 1 , wherein
the PLL further comprises a frequency counter configured to record a frequency value of the output signal, and
the high-port calibration control module is configured to capture the positive and negative frequency values by being further configured to
read a first count accumulated by the frequency counter during the first accumulation time period, wherein the positive frequency value is equal to the first count divided by the accumulation time period, and
read a second count accumulated by the frequency counter during the second accumulation time period, wherein the negative frequency value is equal to the second count divided by the second accumulation time period.
7. The PLL of claim 1 , wherein
the PLL further comprises a coarse tune calibration module configured to coarse tune the VCO that results in the initial output frequency being within a frequency threshold of a target frequency, and
the high-port calibration control module is further configured to calibrate the input modulation value to a center modulation value prior to the coarse tune, wherein the center modulation value is between the first and second modulation values, and the coarse tune is performed prior to calibration of the input modulation value to the first and second modulation values.
8. The PLL of claim 7 , wherein a first plurality of modulation steps between the center modulation value and the first modulation value is equal to a second plurality of modulation steps between the center modulation value and the second modulation value.
9. The PLL of claim 7 , wherein a first plurality of modulation steps between the center modulation value and the first modulation value is not equal to a second plurality of modulation steps between the center modulation value and the second modulation value.
10. The PLL of claim 1 , wherein the first modulation value and the second modulation value are separated by a plurality of modulation steps, and the plurality of modulation steps comprises up to a maximum number of modulation steps available in the high-port modulator.
11. The PLL of claim 1 , wherein the difference between the positive and negative frequency values and a present reference frequency of the VCO are used to perform a lookup for an associated calibration scale factor and an associated frequency scale factor in the lookup table.
12. The PLL of claim 1 , wherein the high-port modulator comprises at least one of a digital-to-analog converter (DAC) and a bank of switchable varactors.
13. The PLL of claim 1 , wherein the modulation signal comprises a plurality of signals.
14. A semiconductor device comprising:
a phase-locked loop (PLL) comprising:
a high-port calibration control module configured to
calibrate an input modulation value of a voltage-controlled oscillator (VCO) to a first modulation value that results in an output signal of the VCO having a positive frequency change from an initial output frequency,
capture positive frequency value of the output signal after a first accumulation time period,
calibrate the input modulation value of the VCO to a second modulation value that results in the output signal having a negative frequency change from the initial output frequency,
capture a negative frequency value of the output signal after a second accumulation time period, and
calculate a calibration scale factor based on a difference between the positive and negative frequency values, including
calculate a change in modulation value equal to a difference between the first and second modulation values;
calculate a change in output frequency equal to a difference between the positive and negative frequency values;
calculate calibration resolution equal to the change in output frequency divided by the change in modulation value; and
calculate the calibration scale factor equal to a low-port modulation resolution divided by the calibration resolution,
wherein the low-port modulation resolution is equal to a reference frequency divided by base 2 raised to a number of modulation steps available in a low-port modulator.
15. The semiconductor of claim 14 , wherein the calibration scale factor is configured to calibrate the input modulation value to a calibrated modulation value that results in the output signal of the VCO having an accurate frequency deviation around a target frequency to which the PLL is locked.
16. The semiconductor device of claim 15 , wherein
the PLL further comprises a sigma-delta modulator configured to receive a low-port modulation value that results in a low-port modulation frequency response at VCO output, and
the calibrated modulation value results in a high-port modulation frequency response at VCO output that is complimentary to the low-port modulation frequency response at VCO output.
17. A method for operating a phase-locked loop (PLL) comprising:
calibrating an input modulation value of a voltage-controlled oscillator (VCO) of the PLL to a first modulation value that results in an output signal of the VCO having a positive frequency change from an initial output frequency,
capturing a positive frequency value of the output signal after a first accumulation time period,
calibrating the input modulation value of the VCO to a second modulation value that results in the output signal having a negative frequency change from the initial output frequency,
capturing a negative frequency value of the output signal after a second accumulation time period, and
calculating a calibration scale factor based on a difference between the positive and negative frequency values, including:
calculating a change in modulation value equal to a difference between the first and second modulation values;
calculating a change in output frequency equal to a difference between the positive and negative frequency values;
calculating calibration resolution equal to the change in output frequency divided by the change in modulation value; and
calculating the calibration scale factor equal to a low-port modulation resolution divided by the calibration resolution,
wherein the low-port modulation resolution is equal to a reference frequency divided by base 2 raised to a number of modulation steps available in a low-port modulator.