Relaxation oscillator
A relaxation oscillator shares charging current and comparator biasing current between just two current sources, thereby relaxing requirements on total supply current. The resulting reduction in power consumption has no adverse effect on the speed and accuracy of the oscillator. A switching arrangement directs charging and biasing currents between the two current sources and two charging capacitors and their associated comparators.
1. An oscillator circuit, comprising:
a flip-flop for generating a clock signal at an output thereof;
first and second current sources;
first and second capacitors;
first and second comparators for comparing a voltage across the first and second capacitors respectively with a reference voltage, wherein each comparator has an output connected to an input of the flip-flop; and
a switching circuit connected to the output of the flip-flop and arranged to direct (i) on a first half cycle of the clock signal, a first charging current to the first capacitor from the first current source and to direct a first biasing current to the first comparator from the second current source, and (ii) on a second half cycle of the clock signal, a second charging current to the second capacitor from the second current source and to direct a second biasing current to the second comparator from the first current source.
2. The oscillator circuit of claim 1 , wherein the flip-flop comprises a SR flip-flop having an R terminal that receives the output of the first comparator, an S terminal that receives the output of the second comparator, a Q terminal that provides the clock signal and a /Q terminal that provides an inverted version of the clock signal.
3. The oscillator circuit of claim 2 , wherein:
the first current source comprises a first PMOSFET having a source terminal that receives a source voltage VDD, a drain terminal connected to the switching circuit, and a gate terminal connected to a bias voltage VB; and
the second current source comprises a second PMOSFET having a source terminal that receives the source voltage VDD, a drain terminal connected to the switching circuit, and a gate terminal connected to the bias voltage VB and to the gate terminal of the first PMOSFET.
4. The oscillator circuit of claim 3 , wherein the switching circuit includes:
a first switch having a source terminal connected to the drain terminal of the first PMOSFET, a drain terminal connected to a first terminal of the first capacitor for providing the first charging current to the first capacitor, and a gate terminal connected to the /Q terminal of the SR flip-flop;
a second switch having a source terminal connected to the drain terminal of the first PMOSFET, a drain terminal connected to a terminal of the second comparator for providing the second bias current thereto, and a gate terminal connected to the /Q terminal of the SR flip-flop by way of a first inverter;
a third switch having a source terminal connected to a supply voltage VSS, a drain terminal connected to the drain terminal of the first switch, and a gate terminal connected to the /Q terminal of the SR flip-flop;
a fourth switch having a source terminal connected to the drain terminal of the second PMOSFET, a drain terminal connected to a terminal of the first comparator for providing the first bias current thereto, and a gate terminal connected to the Q terminal of the SR flip-flop by way of a second inverter;
a fifth switch having source terminal connected to a drain of the first PMOSFET, a drain terminal connected to a first terminal of the second capacitor for providing the second charging current to the second capacitor, and a gate terminal connected to the Q terminal of the SR flip-flop; and
a sixth switch having a source terminal connected to the supply voltage VSS, a drain terminal connected to the drain terminal of the second PMOSFET, and a gate terminal connected to the Q terminal of the SR flip-flop,
wherein, (i) on a first half cycle of the clock signal, the first switch directs the first charging current from the first current source to the first capacitor and the fourth switch directs the first biasing current from the second current source to the first comparator, and (ii) on a second half cycle of the clock signal, the fifth switch directs the second charging current from the second current source to the second capacitor and the second switch directs the second biasing current from the first current source to the second comparator.
5. The oscillator circuit of claim 4 , wherein:
the third switch is connected across the first capacitor; and
the sixth switch is connected across the second capacitor,
wherein both of the third and sixth switches are controlled by the /Q and Q outputs of the flip-flop, respectively, and
wherein the third switch is open and the sixth switch is closed on a first half cycle of the clock signal and the third switch is closed and the sixth switch is open on a second half cycle of the clock signal.
6. The oscillator circuit of claim 5 , wherein the first, second, fourth and fifth switches comprise PMOSFETs and the third and sixth switches comprise NMOSFETs.
7. The oscillator circuit of claim 5 , wherein:
the first comparator has a non-inverting input that receives the first charging current from the drain terminal of the first switch, an inverting terminal that receives a reference voltage VREF, and an output terminal connected to the R terminal of the flip-flop; and
the second comparator has a non-inverting input that receives the second charging current from the drain terminal of the fifth switch, an inverting terminal that receives the reference voltage VREF, and an output terminal connected to the S terminal of the flip-flop.
8. The oscillator circuit of claim 7 , further comprising:
a third current source for providing a first additional supply of current to the first comparator; and
a fourth current source for providing a second additional supply of current to the second comparator.
9. The oscillator circuit of claim 8 , wherein:
the third current source comprises a third PMOSFET having a source terminal connected to the supply voltage VDD, a gate terminal connected to the bias voltage VB, and a drain terminal connected to the input terminal of the first comparator and the drain terminal of the fourth switch; and
the fourth current source comprises a fourth PMOSFET having a source terminal connected to the supply voltage VDD, a gate terminal connected to the bias voltage VB, and a drain terminal connected to the drain terminal of the second switch and the input terminal of the second comparator.
10. The oscillator circuit of claim 1 , wherein the oscillator circuit is implemented in an integrated circuit.
11. An oscillator circuit, comprising:
a flip-flop for generating a clock signal at an output thereof;
first and second current sources;
first and second capacitors;
first and second comparators for comparing a voltage across the first and second capacitors respectively with a reference voltage VREF, wherein each comparator has an output connected to an input of the flip-flop; and
a switching circuit connected to the output of the flip-flop and arranged to direct (i) on a first half cycle of the clock signal, a first charging current to the first capacitor from the first current source and to direct a first biasing current to the first comparator from the second current source, and (ii) on a second half cycle of the clock signal, to direct a second charging current to the second capacitor from the first current source and to direct a second biasing current to the second comparator from the second current source.
12. The oscillator circuit of claim 11 , wherein:
the first current source has an output connected to first and second switches; and
the second current source has an output connected to third and fourth switches,
wherein the first, second, third and fourth switches are controlled by the output of the flip-flop, and
wherein (i) on the first half cycle of the clock signal the first switch directs a charging current from the first current source to the first capacitor and the third switch directs a biasing current from the second current source to the first comparator, and (ii) on the second half cycle of the clock signal, the second switch directs the second charging current from the first current source to the second capacitor and the fourth switch directs the second biasing current from the second current source to the second comparator.
13. The oscillator circuit of claim 12 , further comprising:
a fifth switch connected across the first capacitor; and
a sixth switch connected across the second capacitor,
wherein both of the fifth and sixth switches are controlled by the output of the flip-flop, and
wherein the fifth switch is open and the sixth switch is closed on a first half cycle of the clock signal, and the fifth switch is closed and the sixth switch is open on a second half cycle of the clock signal.
14. The oscillator circuit of claim 11 , wherein the flip-flop comprises a SR flip-flop having an R terminal that receives the output of the first comparator, an S terminal that receives the output of the second comparator, a Q terminal that provides the clock signal and a /Q terminal that provides an inverted version of the clock signal.
15. The oscillator circuit of claim 14 , wherein:
the first current source has a source terminal connected to a source voltage VDD, and a gate terminal connected to a bias voltage VB; and
the second current source has a source terminal connected to the source voltage VDD, and a gate terminal connected to the gate terminal of the first current source and to the bias voltage VB.
16. The oscillator circuit of claim 15 , wherein the switching circuit includes:
a first switch having a source terminal connected to a drain terminal of the first current source, a drain terminal connected to a first terminal of the first capacitor, and a gate terminal connected to the /Q output terminal of the flip-flop;
a second switch having a source terminal connected to the drain terminal of the first current source, a drain terminal connected to a first terminal of the second capacitor, and a gate terminal connected to the /Q output terminal of the flip-flop by way of a first inverter;
a third switch having a source terminal connected to a drain terminal of the second current source, a drain terminal connected to an input terminal of the first comparator, and a gate terminal connected to the Q output terminal of the flip-flop by way of a second inverter; and
a fourth switch having a source terminal connected to the drain terminal of the second current source, a drain terminal connected to an input terminal of the second comparator, and a gate terminal connected to the Q output terminal of the flip-flop,
wherein (i) on the first half cycle of the clock signal the first switch directs the first charging current from the first current source to the first capacitor and the third switch directs the first biasing current from the second current source to the first comparator, and (ii) on the second half cycle of the clock signal, the second switch directs the second charging current from the first current source to the second capacitor and the fourth switch directs the second biasing current from the second current source to the second comparator.
17. The oscillator circuit of claim 16 , wherein the switch circuit further comprises:
a fifth switch connected across the first capacitor; and
a sixth switch connected across the second capacitor,
wherein the fifth switch is controlled by the /Q output of the flip-flop and the sixth switch is controlled by the Q output of the flip-flop, and
wherein the fifth switch is open and the sixth switch is closed on the first half cycle of the clock signal, and the fifth switch is closed and the sixth switch is open on the second half cycle of the clock signal.
18. The oscillator circuit of claim 17 , wherein the first, second, third and fourth switches comprise PMOSFETs and the fifth and sixth switches comprise NMOSFETs.
19. The oscillator circuit of claim 11 , wherein the oscillator is implemented in an integrated circuit.