IP Library Granted Patent US 9,318,409
Granted Patent B1
US 9,318,409 · App. 14/496,870 · Granted Apr 19, 2016

Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit

Inventors: Douglas M. Reber (Austin, TX); Mehul D. Shroff (Austin, TX); Edward O. Travis (Austin, TX)
Assignee: FREESCALE SEMICONDUCTOR, INC.
H01L23/345
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,318,409
App. No.
14/496,870
Granted
Apr 19, 2016
Kind
B1
Abstract

A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information.

Claims (47)

1. A device comprising:

a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information;

a first instantiation of a circuit of the integrated circuit chip, disposed at the first location;

a second detector, comprising an output, disposed at a second location of the integrated circuit chip and configured to determine a second temperature information;

a second instantiation of the circuit, disposed at the second location;

a chip heater, comprising an input to receive a control signal, disposed at the second location of the integrated circuit and configured to heat the second location to change a performance characteristic of the second instantiation to match the performance characteristic of the first instantiation, based upon the control signal; and

a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, a second input coupled to the output of the second detector to receive the second temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon a temperature difference between the first temperature information and the second temperature information.

2. The integrated circuit chip of claim 1 , wherein the chip heater comprises a passive element of the integrated circuit chip.

3. The integrated circuit chip of claim 2 , wherein the passive element comprises one of a resistor of the integrated circuit chip and an inductor of the integrated circuit chip.

4. The integrated circuit chip of claim 1 , wherein the chip heater comprises an active circuit of the integrated circuit chip.

5. The integrated circuit chip of claim 4 , wherein the active circuit comprises one of a switched capacitor circuit, a dummy counter circuit, and a dummy clock tree circuit.

6. The integrated circuit chip of claim 1 , further comprising:

a third detector, comprising an output, disposed at a third location of the integrated circuit chip and configured to determine a third temperature information, wherein the area includes the third location;

wherein the heater controller further comprises a third input coupled to the output of the third detector to receive the third temperature information.

7. The integrated circuit chip of claim 6 , wherein the heater controller comprises a temperature gradient circuit including:

a first input to receive the first temperature information;

a second input to receive the third temperature information; and

logic to determine a temperature gradient based on the first temperature information and the third temperature information, and to determine when the temperature gradient is greater than a threshold, wherein generating the control signal is in response to determining that the temperature gradient is greater than the threshold.

8. The integrated circuit chip of claim 6 , wherein the heater controller comprises a temperature difference circuit including:

a first input to receive the first temperature information;

a second input to receive the second temperature information; and

logic to determine the temperature difference based on the first temperature information and the second temperature information, and to determine when the temperature difference is greater than a threshold, wherein generating the control signal is in response to determining that the temperature difference is greater than the threshold.

9. The integrated circuit chip of claim 1 , wherein the first detector comprises a temperature sensor.

10. The integrated circuit chip of claim 1 , wherein the first detector comprises a power detector.

11. The integrated circuit chip of claim 1 , wherein the heater controller is configured to generate the control signal to reduce physical stress in a semiconductor material of the integrated circuit chip.

12. The integrated circuit chip of claim 1 , wherein the heater controller is configured to generate the control signal to reduce stress in a chip lead of the integrated circuit chip.

13. The integrated circuit chip of claim 1 , wherein the heater controller is configured to generate the control signal to improve the performance characteristic of the circuit.

14. A device comprising:

a first integrated circuit chip attached to a chip carrier, the first integrated circuit having:

a detector, comprising an output, disposed at a first location of the first integrated circuit chip and configured to determine a first temperature information;

a chip heater, comprising an input to receive a control signal, disposed at a second location of the first integrated circuit and configured to heat a first area of the first integrated circuit device that includes the first location and the second location, based upon the control signal; and

a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information; and

a second integrated circuit chip stacked with the first integrated circuit chip, wherein the chip heater is further configured to heat a third location of the second integrated circuit device.

15. The device of claim 14 , wherein the chip heater comprises a passive element of the first integrated circuit chip.

16. The device of claim 14 , wherein the chip heater comprises a circuit of the first integrated circuit chip.

17. The device of claim 14 , wherein the detector comprises at least one of a temperature sensor and a power detector.

18. The device of claim 14 , wherein the heater controller is configured to generate the control signal to reduce physical stress between the first integrated circuit chip and the second integrated circuit chip.

19. The device of claim 14 , wherein the heater controller is configured to generate the control signal to reduce stress in a chip lead between the first integrated circuit chip and the second integrated circuit chip.

20. A method comprising:

determining, by a first detector of an integrated circuit chip disposed at a first location, first temperature information;

locating, at the first location, a first instantiation of a circuit of the integrated circuit;

providing, by the first detector, the first temperature information to a heater controller of the integrated circuit device;

determining, by a second detector of the integrated circuit clip disposed at a second location, second temperature information;

locating, at the second location, a second instantiation of the circuit;

providing, by the second detector, the second temperature information to the heater controller;

generating, by the heater controller a control signal based upon a temperature difference between the first temperature information and the second temperature information; and

heating, by a chip heater of the integrated circuit device disposed at the second location the second instantiation to change a performance characteristic of the second instantiation to match the performance characteristic of the first instantiation in response to the control signal.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0460 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0502 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0921 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034153/0027 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0370 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2014
From: REBER, DOUGLAS M.; SHROFF, MEHUL D.; TRAVIS, EDWARD O.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 033821/0722 →