Patent Assignment
Reel/Frame 034153/0027
SUPPLEMENT TO IP SECURITY AGREEMENT
Recorded: 2014-11-04
Received: 2014-11-04
Pages: 19
Assignor
FREESCALE SEMICONDUCTOR, INC.
Executed: 2014-10-30
Assignee
CITIBANK, N.A., AS NOTES COLLATERAL AGENT
390 GREENWICH STREET, NEW YORK, NY, 10013, UNITED STATES
Covered Applications
(100)
REFERENCE VOLTAGE SOURCE AND METHOD FOR PROVIDING A CURVATURE-COMPENSATED REFERENCE VOLTAGE
App. No. 14/382,559
→
SECURE LOW VOLTAGE TESTING
App. No. 14/502,406
→
SENSED SWITCH CURRENT CONTROL
App. No. 14/502,002
→
ORIENTATION DETERMINATION FOR DEVICES GENERATING ELECTROMAGNETIC INTERFERENCE
App. No. 14/502,393
→
NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM)
App. No. 14/501,781
→
SYSTEMS AND METHODS FOR MANAGING RETURN STACKS IN A MULTI-THREADED DATA PROCESSING SYSTEM
App. No. 14/502,027
→
ACCELEROMETER CALIBRATION IN A ROTATING MEMBER
App. No. 14/501,276
→
FAN-OUT WAFER LEVEL PACKAGES CONTAINING EMBEDDED GROUND PLANE INTERCONNECT STRUCTURES AND METHODS FOR THE FABRICATION THEREOF
App. No. 14/500,698
→
Final Result Checking For System With Pre-Verified Cores
App. No. 14/500,816
→
SUBSTRATE FOR ALTERNATIVE SEMICONDUCTOR DIE CONFIGURATIONS
App. No. 14/499,266
→
FLEXIBLE CIRCUIT LEADS IN PACKAGING FOR RADIO FREQUENCY DEVICES
App. No. 14/500,319
→
MULTI-PARTITION NETWORKING DEVICE AND METHOD THEREFOR
App. No. 14/499,385
→
SEMICONDUCTOR DEVICE AND METHOD OF ASSEMBLING SAME
App. No. 14/499,240
→
MODIFIABLE SIGNAL ADJUSTMENT DEVICES FOR POWER AMPLIFIERS AND CORRESPONDING METHODS & APPARATUS
App. No. 14/500,992
→
SUBSTRATE WITH ELECTRICALLY ISOLATED BOND PADS
App. No. 14/499,264
→
METHOD AND APPARATUS FOR DETECTING A STATE OF AN ALTERNATOR REGULATOR
App. No. 14/496,647
→
INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIRCUIT MATERIAL AND CHIP LEADS OF THE INTEGRATED CIRCUIT, AND FOR OPTIMIZING PERFORMANCE OF DEVICES OF THE INTEGRATED CIRCUIT
App. No. 14/496,870
→
PACKAGED RF AMPLIFIER DEVICES WITH GROUNDED ISOLATION STRUCTURES AND METHODS OF MANUFACTURE THEREOF
App. No. 14/496,477
→
ELECTRONIC FAULT DETECTION UNIT
App. No. 14/496,552
→
SEMICONDUCTOR DEVICE WITH IMPROVED BREAKDOWN VOLTAGE
App. No. 14/495,508
→
ELECTRONIC DEVICE HAVING A RUNTIME INTEGRITY CHECKER
App. No. 14/494,767
→
Differential Pressure Sensor Assembly
App. No. 14/495,095
→
Methods And Systems For Controlling Ordered Write Transactions To Multiple Devices Using Switch Point Networks
App. No. 14/495,096
→
MODULAR GRAY CODE COUNTER
App. No. 14/495,876
→
FAN-OUT WAFER LEVEL PACKAGE CONTAINING BACK-TO-BACK EMBEDDED MICROELECTRONIC COMPONENTS AND ASSEMBLY METHOD THEREFOR
App. No. 14/494,611
→
LOW VOLTAGE SWING BUFFER
App. No. 14/494,976
→
Piggy-Back Snoops For Non-Coherent Memory Transactions Within Distributed Processing Systems
App. No. 14/495,209
→
CIRCUIT FOR TESTING POWER SUPPLIES IN MULTIPLE POWER MODES
App. No. 14/493,347
→
PERFORMANCE BASED POWER MANAGEMENT OF A MEMORY AND A DATA STORAGE SYSTEM USING THE MEMORY
App. No. 14/493,353
→
THREE-AXIS MICROELECTROMECHANICAL SYSTEMS DEVICES
App. No. 14/493,890
→
METHOD FOR RESETTING AN ELECTRONIC DEVICE HAVING INDEPENDENT DEVICE DOMAINS
App. No. 14/492,711
→
COPPER WIRE THROUGH SILICON VIA CONNECTION
App. No. 14/493,332
→
INTERFACE SYSTEM AND METHOD
App. No. 14/492,601
→
VIDEO PROCESSING DEVICE AND METHOD
App. No. 14/492,573
→
INTEGRATED CIRCUIT AND METHOD OF OPERATING AN INTEGRATED CIRCUIT
App. No. 14/492,633
→
INTEGRATION OF A NON-VOLATILE MEMORY (NVM) CELL AND A LOGIC TRANSISTOR AND METHOD THEREFOR
App. No. 14/491,551
→
INTEGRATED CIRCUIT PACKAGE
App. No. 14/490,849
→
MEMORY MANAGEMENT COMPONENT HAVING MULTIPLE MEMORY MANGAGEMENT MODULES AND METHOD THEREFOR
App. No. 14/490,902
→
PACKAGED RF AMPLIFIER DEVICES AND METHODS OF MANUFACTURE THEREOF
App. No. 14/491,574
→
A STRUCTURE FOR A RADIO FREQUENCY POWER AMPLIFIER MODULE WITHIN A RADIO FREQUENCY POWER AMPLIFIER PACKAGE
App. No. 14/489,868
→
RERAM DEVICE STRUCTURE
App. No. 14/490,062
→
METHOD OF VALIDATING TIMING ISSUES IN GATE-LEVEL SIMULATION
App. No. 14/488,313
→
VOLTAGE REGULATION SYSTEM FOR INTEGRATED CIRCUIT
App. No. 14/488,261
→
STARVATION CONTROL IN A DATA PROCESSING SYSTEM
App. No. 14/487,897
→
KEY STORAGE AND REVOCATION IN A SECURE MEMORY SYSTEM
App. No. 14/487,560
→
METHOD AND APPARATUS FOR CONTROL OF A SWITCHED CURRENT CIRCUIT
App. No. 14/486,430
→
DOMAIN NAME COLLABORATION SERVICE USING DOMAIN NAME DEPENDENCY SERVER
App. No. 14/486,584
→
DRAIN-END DRIFT DIMINUTION IN SEMICONDUCTOR DEVICES
App. No. 14/486,104
→
REDUCING THE POWER CONSUMPTION OF MEMORY DEVICES UTILIZING DATA TRANSITION DETECTION
App. No. 14/485,754
→
HIGH VOLTAGE FAILURE RECOVERY FOR EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY SYSTEM
App. No. 14/484,876
→
ADAPTIVE ERROR CORRECTION CODES (ECCs) FOR ELECTRONIC MEMORIES
App. No. 14/485,624
→
MEMORY MANAGEMENT AND METHOD FOR ALLOCATION USING FREE-LIST
App. No. 14/484,515
→
MULTI-CHIP DEVICE WITH TEMPERATURE CONTROL ELEMENT FOR TEMPERATURE CALIBRATION
App. No. 13/511,974
→
MECHANISM FOR MANAGING ACCESS TO AT LEAST ONE SHARED INTEGRATED PERIPHERAL OF A PROCESSING UNIT AND A METHOD OF OPERATING THEREOF
App. No. 14/483,273
→
INTEGRATED CIRCUIT AND METHOD OF DETECTING A DATA INTEGRITY ERROR
App. No. 14/483,262
→
DEVICE AND METHOD FOR COMPENSATING FOR VOLTAGE DROPS
App. No. 14/483,899
→
METHOD AND APPARATUS FOR CONFIGURING I/O CELLS OF A SIGNAL PROCESSING IC DEVICE INTO A SAFE STATE
App. No. 14/482,387
→
SYSTEM FOR TESTING IC DESIGN
App. No. 14/481,899
→
VOLTAGE-DRIVER CIRCUIT WITH DYNAMIC SLEW RATE CONTROL
App. No. 14/480,642
→
REDUCING PACKET REORDERING IN FLOW-BASED NETWORKS
App. No. 14/481,277
→
LOW SWING FLIP-FLOP WITH REDUCED LEAKAGE SLAVE LATCH
App. No. 14/481,269
→
MOLDED INTERPOSER FOR PACKAGED SEMICONDUCTOR DEVICE
App. No. 14/479,377
→
DATA LOGGING SYSTEM AND METHOD
App. No. 14/479,456
→
INTEGRATION OF A NON-VOLATILE MEMORY (NVM) CELL AND A LOGIC TRANSISTOR AND METHOD THEREFOR
App. No. 14/480,017
→
SEMICONDUCTOR DEVICE ATTACHED TO AN EXPOSED PAD
App. No. 14/480,039
→
SEMICONDUCTOR DEVICE WITH PLATED THROUGH HOLES
App. No. 14/477,885
→
MULTIBIT SENSE AMPLIFIER CALIBRATION
App. No. 14/478,320
→
SEMICONDUCTOR SENSOR DEVICE FORMED WITH GEL SHEET
App. No. 14/477,881
→
METHODS AND APPARATUS FOR AN ISFET
App. No. 14/478,149
→
FAN-OUT WAFER LEVEL PACKAGES HAVING PREFORMED EMBEDDED GROUND PLANE CONNECTIONS AND METHODS FOR THE FABRICATION THEREOF
App. No. 14/477,729
→
PIN DIODE WITH NANOCLUSTERS
App. No. 14/476,957
→
METHOD TO FORM SELF-ALIGNED HIGH DENSITY NANOCRYSTALS
App. No. 14/476,827
→
INTERRUPT SUPERVISION SYSTEM, PROCESSING SYSTEM AND METHOD FOR INTERRUPT SUPERVISON
App. No. 14/382,593
→
DEBUG ARCHITECTURE FOR MULTITHREADED PROCESSORS
App. No. 14/475,507
→
NON-HOMOGENEOUS MOLDING OF PACKAGED SEMICONDUCTOR DEVICES
App. No. 14/474,291
→
SEMICONDUCTOR DEVICE PACKAGE WITH ORGANIC INTERPOSER
App. No. 14/474,294
→
TRENCH GATE FET WITH SELF-ALIGNED SOURCE CONTACT
App. No. 14/473,327
→
MULTI-BIT FLIP-FLOP WITH ENHANCED FAULT DETECTION
App. No. 14/472,809
→
EDGE TERMINATION FOR TRENCH GATE FET
App. No. 14/473,358
→
PACKAGE SUBSTRATE WITH IMPROVED RELIABILITY
App. No. 14/472,836
→
RADIO FREQUENCY COUPLING STRUCTURE AND A METHOD OF MANUFACTURING THEREOF
App. No. 14/473,038
→
WARP COMPENSATED ELECTRONIC ASSEMBLIES
App. No. 14/474,063
→
SWITCHING SCHEME TO EXTEND MAXIMUM INPUT VOLTAGE RANGE OF A DC-TO-DC VOLTAGE CONVERTER
App. No. 14/472,903
→
STRUCTURE AND METHOD TO MINIMIZE WARPAGE OF PACKAGED SEMICONDUCTOR DEVICES
App. No. 14/472,882
→
WETTING CURRENT DIAGNOSTICS
App. No. 14/473,799
→
SYSTEMS THAT INCLUDE MICROWAVE ADAPTORS AND METHODS OF THEIR OPERATION
App. No. 14/474,062
→
FLASH MEMORY EXPRESS ERASE AND PROGRAM
App. No. 14/473,418
→
Command Set Extension for Non-Volatile Memory
App. No. 14/471,871
→
ELECTRIC POWER METER
App. No. 14/471,107
→
WIRELESS COMMUNICATION UNIT, INTEGRATED CIRCUITS AND METHOD FOR LINEARIZING A TRANSMITTER SIGNAL
App. No. 14/469,916
→
METHODS AND APPARATUS FOR DETECTING SOFTWARE INTEFERENCE
App. No. 14/469,775
→
FLASH MEMORY WITH IMPROVED READ PERFORMANCE
App. No. 14/470,359
→
SEMICONDUCTOR MEMORY CELL AND DRIVER CIRCUITRY WITH GATE OXIDE FORMED SIMULTANEOUSLY
App. No. 14/470,374
→
APPARATUS AND METHOD FOR VALIDATING THE INTEGRITY OF CONTROL SIGNALS IN TIMING DOMAIN
App. No. 14/469,740
→
MICROELECTRONIC PACKAGES HAVING TEXTURIZED SOLDER PADS AND METHODS FOR THE FABRICATION THEREOF
App. No. 14/470,679
→
SEMICONDUCTOR MANUFACTURING FOR FORMING BOND PADS AND SEAL RINGS
App. No. 14/470,383
→
LOW SIDE AND HIGH SIDE DRIVERS FOR A MOTOR
App. No. 14/470,027
→
LOW RESISTANCE POLYSILICON STRAP
App. No. 14/470,894
→
SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFACTURING SAME
App. No. 14/469,645
→
INTEGRATED CIRCUIT DEVICE AND METHOD OF PERFORMING SELF-TESTING WITHIN AN INTEGRATED CIRCUIT DEVICE
App. No. 14/468,917
→