IP Library Patent Application 14479377
Patent Application
App. No. 14/479,377

MOLDED INTERPOSER FOR PACKAGED SEMICONDUCTOR DEVICE

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Patent No.
US None
App. No.
14/479,377
Abstract

A method for forming a pass-through layer of an interposer of a packaged semiconductor device in which conducting structures are extended between first and second ends of a casing. The conducting structures are subsequently encapsulated in a molding compound to form a molded bar, and the molded bar is sliced to obtain the pass-through layer. The pass-through layer has conducting vias, each corresponding to a sliced section of one of the conducting structures. The cost of pass-through layers formed in this manner may be less than that of comparable silicon or glass pass-through layers.

Claims (18)

1 - 4 . (canceled)

5 . A method of assembling a semiconductor device, comprising:

(a) extending, in a casing comprising a first end and a second end, a plurality of conducting structures between the first and second ends;

(b) encapsulating the conducting structures in a molding compound to form a molded bar;

(c) slicing the molded bar to obtain a pass-through layer for an interposer of a packaged semiconductor device, wherein the pass-through layer comprises a plurality of conducting vias, each conducting via corresponding to a sliced section of one of the conducting structures, a first surface, and a second surface parallel to the first surface, wherein each of the conducting vias extends between the first and second surfaces; and

(f) masking and etching the pass-through layer to form bond pads on the first and second surfaces.

6 . The method of claim 5 , wherein step (c) comprises slicing the molded bar multiple times to obtain a plurality of pass-through layers for a plurality of interposers of a plurality of packaged semiconductor devices.

7 . The method of claim 5 ,

further comprising (d) forming the interposer by depositing a first redistribution layer on the first surface of the pass-through layer.

8 . The method of claim 7 , further comprising (e) depositing a second redistribution layer on the second surface of the pass-through layer.

9 . The method of claim 7 , further comprising (e) forming a plurality of conducting leads on a bottom surface of the interposer.

10 . The method of claim 7 , wherein step (d) comprises:

(d1) assembling the pass-through layer and a plurality of other pass-through layers into a reconstituted wafer form; and

(d2) forming an instance of the first redistribution layer on each of the pass-through layer and the other pass-through layers while the pass-through layer and plurality of other pass-through layers are in the reconstituted wafer form.

11 . The method of claim 10 , further comprising (e) assembling the packaged semiconductor device, wherein step (e) comprises:

(e1) mounting at least one integrated circuit (IC) die onto the interposer and electrically coupling the IC die to one or more of the conducting vias; and

(e2) mounting the interposer onto a substrate and electrically coupling one or more of the plurality of conducting vias to the substrate.

12 . A packaged semiconductor assembled using the method of claim 5 .

Assignments (11)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0460 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0502 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0921 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0370 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0351 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034153/0027 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2014
From: TONG, PEI FAN; LOW, BOON YEW; TAN, LAN CHU
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 033694/0058 →