Semiconductor package with embedded capacitor and methods of manufacturing same
View Patent ↗A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.
1. A method of manufacturing a semiconductor package with an embedded capacitor, the method comprising:
forming a dielectric layer of a package structure onto a first metal layer of a semiconductor die;
forming, from the dielectric layer, a dielectric of the embedded capacitor, wherein the dielectric is positioned vertically adjacent to a first electrical conductor of the embedded capacitor, wherein the first electrical conductor is formed in the first metal layer of the semiconductor die;
forming a second metal layer of the package structure onto the dielectric of the embedded capacitor;
forming, from the second metal layer, a second electrical conductor of the embedded capacitor, wherein
the second electrical conductor is positioned vertically adjacent to the dielectric of the embedded capacitor, and
said forming the second electrical conductor comprises forming a second landing member and a pair of extension members that connect the second landing member to a pair of voltage pads formed in the first metal layer of the semiconductor die, wherein the second landing member overlaps a first landing member of the first electrical conductor of the embedded capacitor, and the dielectric of the embedded capacitor is between the first and second landing members.
2. The method of manufacturing a semiconductor package of claim 1 , wherein forming the dielectric layer comprises forming a high-k dielectric layer.
3. The method of manufacturing a semiconductor package of claim 1 , wherein the dielectric layer and the second metal layer are formed as part of a wafer level package build-up process.
4. The method of manufacturing a semiconductor package of claim 3 , wherein the wafer level package build-up process is a fan-out wafer level package build-up process.
5. The method of manufacturing a semiconductor package of claim 4 , wherein the second metal layer is an initially-formed metal layer of multiple metal layers formed during the fan-out wafer level package build-up process.