IP Library Granted Patent US 9,665,518
Granted Patent B2
US 9,665,518 · App. 14/495,096 · Granted May 30, 2017

Methods and systems for controlling ordered write transactions to multiple devices using switch point networks

Inventors: Sanjay R. Deshpande (Austin, TX); Mark A. Banse (Austin, TX); John E. Larson (Round Rock, TX); Fernando A. Morales (Austin, TX); Thang Q. Nguyen (Austin, TX)
Assignee: NXP USA, Inc.
G06F13/4022G06F13/1621
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Quick Facts
Patent No.
US 9,665,518
App. No.
14/495,096
Granted
May 30, 2017
Kind
B2
Abstract

Ordered write transactions from requester devices to multiple target devices are controlled using switch point networks. The requester device and the multiple target devices for the write transactions are coupled to a network of interconnected switch points. Write requests are generated for a plurality of parcels associated with a block of data to be written. The write requests have a particular order associated with an order in which the parcels are to be written, and these write requests are provided to the switch point interconnection network in the particular order. At least one of the switch points is then used to control the flow of write requests to the multiple target devices such that the particular order is maintained. In one embodiment, the target devices are memory devices, and the particular order is based upon the AXI (Advanced eXtensible Interface) protocol.

Claims (39)

1. A method to control ordered writes of data from a requester device to multiple target devices, comprising:

generating a plurality of write requests for a plurality of parcels associated with a block of data to be written from a requester device to multiple target devices, the write requests having a particular order in which the parcels are to be written to the multiple target devices;

sending the write requests to a network of a plurality of interconnected switch points in the particular order, the requester device and the multiple target devices being coupled to the plurality of interconnected switch points; and

controlling flow of the write requests to the multiple target devices using at least one of the switch points such that the particular order is maintained, wherein each write request comprises a requester identifier field for the requester device, a transaction identifier field for the target device, and at least one order bit indicating whether the particular oder is to be enforced.

2. The method of claim 1 , further comprising storing a requester identifier and a transaction identifier for each of the write requests within the at least one switch point.

3. The method of claim 1 , wherein the controlling comprises holding one or more second write requests for a second target device until one or more first write requests for a first target device have completed if the particular order indicates that the second write requests are to occur after the first write requests.

4. The method of claim 1 , wherein the plurality of interconnected switch points are arranged in an array having a plurality of rows and a plurality of columns, and wherein each switch point is connected to switch points in adjacent rows and columns.

5. The method of claim 4 , wherein the requester device and each of the target devices are coupled to a different switch point, and wherein the at least one switch point comprises a switch point within the plurality of switch points that has a least number of switch points between itself and the switch points coupled to the target devices.

6. The method of claim 1 , further comprising receiving write completion responses from the target devices when write requests are completed by the target devices.

7. The method of claim 6 , further comprising combining a plurality of write completion responses into a combined write complete response.

8. The method of claim 1 , wherein the target devices comprise memory devices, and wherein the particular order is based upon the AXI (Advanced eXtensible Interface) protocol.

9. A method to control ordered writes of data from a requester device to multiple target devices, comprising:

generating a plurality of write requests for a plurality of parcels associated with a block of data to be written from a requester device to multiple target devices, the write requests having a particular order in which the parcels are to be written to the multiple target devices;

sending the write requests to a network of a plurality of interconnected switch points in the particular order, the requester device and the multiple target devices being coupled to the plurality of interconnected switch points; and

controlling flow of the write requests to the multiple target devices using at least one of the switch points such that the particular order is maintained;

receiving write completion responses from the target devices when write requests are completed by the target devices; and

setting at least one bit in a last write request to indicate that it holds a last parcel in the particular order, and setting at least one bit in a last write completion response to indicate that it is associated with the last parcel in the particular order.

10. The method of claim 9 , wherein the controlling comprises holding one or more second write requests for a second target device until one or more first write requests for a first target device have completed if the particular order indicates that the second write requests are to occur after the first write requests.

11. The method of claim 9 , wherein the plurality of interconnected switch points are arranged in an array having a plurality of rows and a plurality of columns, and wherein each switch point is connected to switch points in adjacent rows and columns.

12. The method of claim 9 , wherein the target devices comprise memory devices, and wherein the particular order is based upon the AXI (Advanced eXtensible Interface) protocol.

13. An interconnect system to control ordered writes of data from a requester device to multiple target devices, comprising:

a plurality of interconnected switch points, at least one of the switch points being coupled to a requester device, at least one of the switch points being coupled to a first target device, and at least one of the switch points being coupled to a second target device;

at least one controlling switch point within the plurality of interconnected switch points coupled to receive write requests for a plurality of parcels associated with a block of data to be written from the requester device to the first and second target devices, the write requests having a particular order in which the parcels are to be written to the multiple target devices; and

a controller within the controlling switch point coupled to receive the write requests and to control flow of the write requests to the first and second target devices such that the particular order is maintained, wherein each write request comprises a requester identifier field for the requester device, a transaction identifier field for the target device, and at least one order bit indicating whether the particular order is to be enforced.

14. The interconnect system of claim 13 , further comprising a plurality of transaction counters within the controlling switch point, each transaction counter being configured to store a requester identifier and a transaction identifier for each of the write requests.

15. The interconnect system of claim 13 , wherein the controller within the controlling switch point is coupled to receive one or more second requests for the second target device, to receive one or more first requests for the first target device, and to hold the second write requests until the first write requests have completed if the particular order indicates that the second write requests are to occur after the first write requests.

16. The interconnect system of claim 13 , wherein the plurality of switch points are arranged in an array having a plurality of rows and a plurality of columns, and wherein each switch point is connected to switch points in adjacent rows and columns.

17. The interconnect system of claim 16 , wherein the requester device and the first and second target devices are coupled to a different switch point, and wherein the controlling switch point comprises a switch point within the plurality of switch points that has a least number of switch points between itself and the switch points coupled to the target devices.

18. The interconnect system of claim 13 , wherein the controlling switch point is further configured to receive write completion responses from the first and second target devices when write requests are completed by the first and second target devices.

19. The interconnect system of claim 18 , wherein the least one of the switch point coupled to the requester device is configured to receive the write completion responses and to combine them into a combined write complete response.

20. The interconnect system of claim 13 , wherein the first and second target devices comprise memory devices, and wherein the particular order is based upon the AXI (Advanced eXtensible Interface) protocol.

21. An interconnect system to control ordered writes of data from a requester device to multiple target devices, comprising:

a plurality of interconnected switch points, at least one of the switch points being coupled to a requester device, at least one of the switch points being coupled to a first target device, and at least one of the switch points being coupled to a second target device;

at least one controlling switch point within the plurality of interconnected switch points coupled to receive write requests for a plurality of parcels associated with a block of data to be written from the requester device to the first and second target devices, the write requests having a particular order in which the parcels are to be written to the multiple target devices; and

a controller within the controlling switch point coupled to recieve the write requests and to control flow of the write requests to the first and second target devices such the the particular order is maintained;

wherein the controlling switch point is further configured to received write completion responses from the first and second target devices when write requests are completed by the first and second target devices, and, wherein at least one bit in the write requests is configured to indicate that it holds a last parcel in the particular order, and wherein at least one bit in a last write completion response is configured to indicate that it is associated with the last parcel in the particular order.

22. The interconnect system of claim 21 , wherein the controllor within the controlling switch point is coupled to receive one or more second requests for the second target device, to receive one or more first requests for the first target device, and to hold the second write requests until the first write requests have completed if the particular order indicates that the second write requests are to occur after the first write requests.

23. The interconnect system of claim 21 , wherein the plurality of switch points are arranged in an array having a plurality of rows and a plurality of columns, and wherein each switch point is connected to switch points in adjacent rows and columns.

24. The interconnect system of claim 21 , wherein the first and second target devices comprise memory devices, and wherein the particular order is based upon the AXI (Advanced eXtensible Interface) protocol.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0502 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0460 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0921 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034153/0027 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0351 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0370 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014
From: DESHPANDE, SANJAY R.; BANSE, MARK A.; LARSON, JOHN E.; MORALES, FERNANDO A.; NGUYEN, THANG Q.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 033807/0576 →
Continuity (1)
Related Publication 20160085706A1 · Mar 24, 2016