Low resistance polysilicon strap
A low resistance polysilicon (poly) structure includes a first poly coupled to a substrate and having a sidewall. A second poly is separated from the sidewall of the first poly and the substrate by a programming oxide. The first poly and the second poly have substantially a same planarized height above the substrate. The first poly extends from a device region to a strap region, and extends substantially parallel to a first length of the second poly. A second length of the second poly extends away from the first poly in the strap region and includes a salicide. A first diffusion region crosses the first poly and the second poly in the device region. A masked width of the first length of the second poly is defined by an etched spacer. A low resistance contact is coupled to the second length of the second poly in the strap region.
1. A method for manufacturing a low resistance polysilicon (poly) strap comprising:
fabricating a structure including a programming oxide separating a first poly from a second poly, the second poly separating the programming oxide from an insulator, the first poly extending from a device region to a strap region, the first poly extending substantially parallel to a first length of the second poly, a second length of the second poly extending away from the first poly in the strap region, and a first diffusion region crossing the first poly and the second poly in the device region;
etching the insulator to form a spacer, the spacer defining a masked width of the first length of the second poly;
etching the second poly excluded by the spacer in the device region to a first depth to leave the masked width of the first length of the second poly and etching the second poly excluded by a mask in the strap region to leave the second length of the second poly;
forming a salicide on at least the second length of the second poly;
planarizing the first poly and the second poly to a second depth by substantially removing the spacer; and
forming a contact with the second length of the second poly in the strap region.
2. The method of claim 1 wherein fabricating the structure includes fabricating in an embedded memory process.
3. The method of claim 1 wherein the fabricating the structure includes fabricating in a high-K metal gate process.
4. The method of claim 1 wherein fabricating the structure includes patterning the first poly with a lithographic feature size of no more than 28 nanometers.
5. The method of claim 1 wherein planarizing includes polishing with a chemical mechanical polish.
6. The method of claim 1 further comprising forming a nitride cap on a top surface of the first poly.
7. A method for manufacturing a low resistance polysilicon (poly) strap comprising:
fabricating a structure including a programming oxide separating a first poly from a second poly, the second poly separating the programming oxide from an insulator, the first poly extending from a device region to a strap region, the first poly extending substantially parallel to a first length of the second poly, a second length of the second poly extending away from the first poly in the strap region, and a first diffusion region crossing the first poly and the second poly in the device region;
etching the insulator to form a spacer, the spacer defining a masked width of the first length of the second poly;
partially etching the second poly to an etch-back depth;
etching the second poly excluded by the spacer in the device region to a first depth to leave the masked width of the first length of the second poly and etching the second poly excluded by a mask in the strap region to leave the second length of the second poly;
forming a salicide on at least the second length of the second poly;
planarizing the first poly and the second poly to a second depth by substantially removing the spacer; and
forming a contact with the second length of the second poly in the strap region.
8. The method of claim 7 wherein fabricating the structure includes fabricating in an embedded memory process with logic devices.
9. The method of claim 7 wherein the fabricating the structure includes fabricating in a high-K metal gate process.
10. The method of claim 7 wherein planarizing includes polishing with a chemical mechanical polish.