Granted Patent B2

US 9,529,047 · App. 14/468,917 · Granted Dec 27, 2016

Abstract

Claims (40)

1. An IC device comprising:

a plurality of functional components arranged into a set of self-test cells;

the IC device being configurable into a first self-test configuration comprising a first set of self-test partitions, the first set of self-test partitions comprising the set of self-test cells;

each self-test partition within the first set of self-test partitions comprising at least one self-test cell, wherein functional components of the at least one self-test cell of each self-test partition within the first set of self-test partitions are arranged to be configured into at least one scan-chain for the respective self-test partition when the IC device is configured into the first self-test configuration;

the IC device being configurable into at least one further self-test configuration comprising at least one further set of self-test partitions, the at least one further set of self-test partitions comprising the set of self-test cells;

each self-test partition within the at least one further set of self-test partitions comprising at least one self-test cell, wherein functional components of the at least one self-test cell of each self-test partition within the at least one further set of self-test partitions are arranged to be configured into at least one scan-chain for the respective self-test partition when the IC device is configured into the at least one further self-test configuration,

wherein no two self-test cells of the set of self-test cells are within a same self-test partition of the first set of self-test partitions and a same self-test partition of the at least one further set of self-test partitions.

2. The IC device of claim 1 , wherein all self-test cells form parts of self-test partitions within at least the first set of self-test partitions.

3. The IC device of claim 1 , wherein all self-test cells form parts of self-test partitions within at least one of the first set of self-test partitions and the at least one further set of self-test partitions.

4. The IC device of claim 1 , wherein no more than one self-test cell within each self-test partition of the first set of self-test partitions does not form a part of a self-test partition of the at least one further set of self-test partitions.

5. The IC device of claim 1 , wherein the IC device comprises a first set of stimulus generator components arranged to execute self-tests within the scan-chains of the first set of self-test partitions and at least one further set of stimulus generator components arranged to execute self-tests within the scan-chains of the at least one further set of self-test partitions.

6. The IC device of claim 1 , wherein the IC device comprises a first set of signature analyzer components arranged to capture signatures output from the scan-chains of the first set of self-test partitions and at least one further set of signature analyzer components arranged to capture signatures output from the scan-chains of the at least one further set of self-test partitions.

7. The IC device of claim 1 , wherein each functional component to be tested by way of a built-in test mechanism of the IC device forms part of a self-test cell and each self-test cell comprises at least one functional component.

8. The IC device of claim 1 , wherein the functional components within self-test cells are arranged to be isolated from functional components within other self-test cells not forming part of a scan-chain therewith during self-test execution.

9. The IC device of claim 1 , wherein the IC device comprises at least one self-test control component arranged to configure the IC device into self-test configurations; wherein the at least one self-test control component is arranged to output a self-test configuration selection signal to selectively configure functional components within the self-test cells into scan-chains for self-test partitions within the first and at least one further set of self-test partitions.

10. The IC device of claim 9 , wherein the at least one self-test control component is further arranged to control stimulus generator components of the first and at least one further set of self-test partitions to execute self-tests within the scan-chains of the respective self-test partitions.

11. The IC device of claim 10 , wherein the at least one self-test control component is further arranged to receive self-test result indications output by signature analyzer components of the first and at least one further set of self-test partitions.

12. The IC device of claim 9 , wherein the at least one self-test control component is further arranged to receive self-test result indications output by signature analyzer components of the first and at least one further set of self-test partitions.

13. The IC device of claim 9 , wherein the at least one self-test control component is arranged to:

configure the IC device into the first self-test configuration;

cause at least one self-test to be executed within the at least one scan-chain for each self-test partition within the first set of self-test partitions;

receive self-test result indications for signatures output by at least one signature analyzer component for each self-test partition within the first set of self-test partitions in response to the execution of at least one self-test therein;

determine whether at least one partition failed the self-test based on the received self-test result indications for signatures output by the at least one signature analyzer component for each self-test partition within the first set of self-test partitions,

wherein the at least one self-test control component is further arranged to, if it is determined that at least one partition failed the self-test:

configure the IC device into the at least one further self-test configuration;

cause at least one self-test to be executed within the at least one scan-chain for each self-test partition within the at least one further set of self-test partitions;

receive self-test result indications for signatures output by at least one signature analyzer component for each self-test partition within the at least one further set of self-test partitions in response to the execution of at least one self-test therein; and

detect a presence of self-test cells comprising at least one defective functional component based on the received self-test result indications for the first and at least one further sets of self-test partitions.

14. The IC device of claim 1 , wherein all self-test cells form parts of self-test partitions within at least the first set of self-test partitions.

15. The IC device of claim 1 , wherein all self-test cells form parts of self-test partitions within at least one of the first set of self-test partitions and the at least one further set of self-test partitions.

16. A method for self-testing a plurality of functional components within an IC device, the plurality of functional components arranged into a set of self-test cells and the method comprising:

configuring the IC device into a first self-test configuration comprising a first set of self-test partitions, the first set of self-test partitions comprising the set of self-test cells and each self-test partition within the first set of self-test partitions comprising at least one self-test cell, wherein functional components of the at least one self-test cell of each self-test partition within the first set of self-test partitions are configured into at least one scan-chain for the respective self-test partition;

executing at least one self-test within the at least one scan-chain for each self-test partition within the first set of self-test partitions;

analyzing signatures output by the at least one signature analyzer component for each self-test partition within the first set of self-test partitions in response to the execution of at least one self-test therein; and

determining whether at least one partition failed the self-test based on the signature analysis for the first set of self-test partitions,

wherein the method further comprises, if it is determined that at least one partition failed the self-test:

configuring the IC device into at least one further self-test configuration comprising at least one further set of self-test partitions, the at least one further set of self-test partitions comprising the set of self-test cells and each self-test partition within the at least one further set of self-test partitions comprising at least one self-test cell, wherein functional components of the at least one self-test cell of each self-test partition within the at least one further set of self-test partitions are configured into at least one scan-chain for the respective self-test partition and wherein no two self-test cells of the set of self-test cells are within a same self-test partition of the first set of self-test partitions and a same self-test partition of the at least one further set of self-test partitions;

executing at least one self-test within the at least one scan-chain for each self-test partition within the at least one further set of self-test partitions;

analyzing signatures output by the at least one signature analyzer component for each self-test partition within the at least one further set of self-test partitions in response to the execution of at least one self-test therein; and

identifying each self-test cell comprising at least one defective functional component based on the signature analysis for the first and at least one further sets of self-test partitions.

Assignments (15)