Multi-bit flip-flop with enhanced fault detection
A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.
1. A processing system, comprising:
a processor core;
a peripheral component;
a flip-flop unit in at least one of the processor core and the peripheral component, the flip-flop unit including:
a master latch;
a first slave latch coupled to an output of the master latch, wherein the first slave latch is formed over a first doped well region of a semiconductor substrate;
a second slave latch coupled to the output of the master latch, wherein the second slave latch is formed over a second doped well region of the semiconductor substrate; and
a comparator coupled to an output of the first slave latch and to an output of the second slave latch, wherein an output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.
2. The system of claim 1 , wherein the master latch is formed over the first doped well region.
3. The system of claim 1 , wherein the second slave latch is positioned at a distance greater than a closest possible distance from the master latch.
4. The system of claim 1 , wherein the first slave latch and the master latch are positioned in a first standard cell and the second slave latch is positioned in a second standard cell at a farthest possible distance from the first slave latch and the master latch.
5. The system of claim 1 , further comprising a fault bus, wherein the output of the comparator is coupled to the fault bus.
6. The system of claim 5 , wherein the flip-flop unit further includes a plurality of: master latches, first and second slave latches, and comparators, and the output from the comparator and a plurality of outputs from the plurality of comparators are coupled to the fault bus.
7. The system of claim 6 , wherein the fault bus is coupled to a detection register with a level shifter to amplify the output from the comparator and the plurality of outputs from the plurality of comparators.
8. The system of claim 5 , wherein the fault bus is connected to end cap cells at both ends of a standard cell row.
9. The system of claim 8 , wherein one of the end cap cells includes a pull-down device to enable wire-ORing of multiple fault signals, and the system further comprises a controlled pull-up device to allow fault injection during testing.
10. The system of claim 5 , further comprising:
a fault collection and control unit coupled to the fault bus, wherein a fault indication is set when one of a group consisting of:
the state stored in the first slave latch is not the same as the state stored in the second slave latch, and the output of the master latch is input to the second slave latch, and
the state stored in the first slave latch is the complement of the state stored in the second slave latch, and the output of the master latch is inverted before being input to the second slave latch.
11. The system of claim 10 , further comprising:
a system control unit coupled between the fault collection and control unit and the processor core, and between the fault collection and control unit and the peripheral, wherein the fault indication from the fault collection and control unit indicates a location of a fault and the system control unit takes corrective action based on the location of the fault indication.
12. A flip-flop unit including:
a plurality of master latches formed over a first doped well region of a semiconductor substrate;
a plurality of first slave latches coupled to an output of a respective one of the master latches, wherein the first slave latch is formed over the first doped well region;
a plurality of second slave latches coupled to the output of the respective one of the master latches, wherein the second slave latch is formed over a second doped well region of the semiconductor substrate; and
a plurality of comparators, each comparator is coupled to an output one of the plurality of first slave latches and to an output of one of the plurality of the second slave latches, wherein an output of each of the comparators indicates whether a state stored in the one of the plurality of first slave latch is the same as a state stored in the one of the plurality of the second slave latch;
a fault bus, wherein the output of each of the comparators is coupled to the fault bus.
13. The flip-flop unit of claim 12 , wherein each of the plurality of the first slave latches and the master latches are positioned in a respective first standard cell and each of the plurality of the second slave latches is positioned in a second standard cell, the second standard cell is at a farthest possible distance from the first slave latch and the flip-clop circuit.
14. The flip-flop unit of claim 12 , wherein the fault bus is coupled to a detection register with a level shifter to amplify the output from the outputs of the plurality of comparators.
15. The flip-flop unit of claim 12 , wherein the fault bus is connected to an end cap cell at one end and the end cap cell includes a pull-down device to enable wire-ORing of multiple fault signals, and the flip-flop unit further comprises a controlled pull-up device to allow fault injection during testing.
16. The flip-flop unit of claim 12 , wherein the plurality of comparators are positioned between the plurality of master latches and the plurality of second slave latches.
17. The flip-flop unit of claim 12 , wherein:
a first half of the plurality of master latches and first slave latches are positioned in a first column of a layout and a first half of the second slave latches associated with the first half of the plurality of master latches and first slave latches are in a second column of the layout; and
a second half of the plurality of master latches and first slave latches are positioned in the second column of the layout and a second half of the second slave latches associated with the second half of the plurality of master latches and first slave latches are in the first column of the layout.
18. A method comprising:
storing an output from a master latch as a state in a first slave latch;
storing the output from the master latch as a state in a second slave latch, wherein the first slave latch and the master latch are implemented using a first doped well of a semiconductor substrate, and the second slave latch is implemented using a second doped well of the semiconductor substrate;
comparing the state stored in the first slave latch to the state stored in the second slave latch;
providing a fault indicator based on whether the state stored in the first slave latch matches the state stored in the second slave latch.
19. The method of claim 18 , further comprising taking corrective action in a processing system component based on the fault indicator.
20. The method of claim 18 , further comprising:
coupling a plurality of fault indicators to a fault bus; and
level shifting the plurality of fault indicators to translate a reduced voltage level on the fault bus to a full voltage level.