Semiconductor device with plated through holes
A semiconductor device package such a as Ball Grid Array (BGA), includes a die attached to a substrate. The substrate has a series of plated through holes (PTH) that include a copper pad at each of their ends. The PTH are located in a mold gate region at a corner of the substrate beyond the periphery of the die. Each PTH contains a rivet. The PTH with the pads and rivets stabilize the substrate at the mold gate region, which reduces the possibility of substrate delamination upon degating following an encapsulation process.
1. A semiconductor device package comprising:
a substrate; and
a die mounted on the substrate, wherein the substrate includes a peripheral region extending beyond a periphery of the die and defining a mold gate region and wherein the mold gate region includes at least one plated through hole; and
a pad formed at each end of the plated through hole.
2. The semiconductor device package of claim 1 , wherein a plurality of plated through holes is located in the mold gate region.
3. The semiconductor package of claim 1 , wherein the plated through hole is electroplated with copper and wherein said pads are copper.
4. The semiconductor device package of claim 1 , wherein the through hole contains a rivet.
5. The semiconductor device package of claim 1 , wherein the die is encapsulated in a molding compound.
6. The semiconductor device package of claim 1 , wherein the substrate is a copper clad laminate.
7. The semiconductor device package of claim 1 , wherein at least a portion of a surface of the mold gate region is plated with a conductive metal.
8. A semiconductor device package, comprising:
a substrate;
a die mounted on the substrate, wherein the substrate includes a peripheral region extending beyond a periphery of the die and defining a mold gate region and wherein the mold gate region includes at least one through hole; and
a rivet formed at least at one end of the through hole.
9. The semiconductor device package of claim 8 , wherein a plurality of through holes is located in the mold gate region of the die, each of the through holes containing rivets.
10. The semiconductor device package of claim 8 , wherein the die is encapsulated in a molding compound.
11. The semiconductor device package of claim 8 , wherein the substrate is a copper clad laminate.
12. The semiconductor device package of claim 8 , wherein at least a portion of a surface of the mold gate region is plated with a conductive metal.
13. A method for manufacturing a semiconductor device package, the method comprising:
mounting a die on a substrate so that a peripheral region of the substrate extends beyond the die to form a mold gate region; and
drilling at least one through hole in the mold gate region to produce a drilled, substrate-die arrangement.
14. The method of claim 13 , comprising:
electroplating the at least one drilled through hole and forming conducting pads at each end thereof on upper and lower surfaces of the mold gate region.
15. The method of claim 13 , comprising inserting a rivet into the at least one drilled through hole.
16. The method of claim 13 , further comprising:
placing a plurality of drilled substrate-die arrangements in a mold;
filling the mold with encapsulating material;
curing the encapsulating material;
removing the mold to leave an array of encapsulated devices connected together by a molding cull; and
removing the molding cull using a degating process.