Drain-end drift diminution in semiconductor devices
View Patent ↗A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.
1. A method of fabricating a transistor, the method comprising:
forming a field isolation region in a substrate;
after forming the field isolation region, implanting dopant in a first region of a substrate for formation of a drift region such that the drift region includes a section under the field isolation region;
forming a drain region in a second region of the substrate;
wherein the first and second regions laterally overlap to define a conduction path for the transistor, and
wherein the first region does not extend laterally across the second region.
2. The method of claim 1 , further comprising forming a doped buried isolation layer in the substrate that extends across an active area of the transistor to act as a barrier that isolates the transistor from a remainder of the semiconductor substrate.
3. The method of claim 1 , further comprising forming an epitaxial layer of the substrate in which the field isolation region is formed.
4. The method of claim 1 , further comprising:
forming an epitaxial layer of the substrate in which the field isolation region is formed; and
forming a doped buried isolation layer in the substrate that extends across an active area of the transistor to act as a barrier that isolates the transistor from a remainder of the semiconductor substrate.
5. The method of claim 1 , wherein:
the substrate does not have a silicon-on-insulator (SOI) construction; and
implanting the dopant in the first region comprises implanting the dopant in an epitaxial layer of the substrate.
6. The method of claim 1 , wherein the drift region has a lateral length of approximately 5 microns or more.
7. A method of fabricating a transistor, the method comprising:
implanting dopant in a first region of a substrate for formation of a drift region, the substrate not having a silicon-on-insulator (SOI) construction;
forming a drain region in a second region of the substrate;
wherein the first and second regions laterally overlap to define a conduction path for the transistor, and
wherein the first region does not extend laterally across the second region.
8. The method of claim 7 , further comprising, before implanting the dopant for formation of the drift region, forming a field isolation region in the substrate such that the drift region includes a section under the field isolation region.
9. The method of claim 8 , wherein the dopant for the formation of the drift region is implanted adjacent the field isolation region such that the field isolation region further defines the conduction path for the transistor.
10. The method of claim 7 , further comprising, after implanting the dopant for formation of the drift region, forming a field isolation region in the substrate such that the drift region includes a section under the field isolation region.
11. The method of claim 7 , wherein the first region is disposed in an epitaxial layer of the substrate.
12. The method of claim 7 , further comprising forming an epitaxial layer of the substrate, wherein implanting the dopant in the first region comprises implanting the dopant in the epitaxial layer.
13. The method of claim 7 , further comprising forming a doped buried isolation layer in the substrate that extends across an active area of the transistor to act as a barrier that isolates the transistor from a remainder of the semiconductor substrate.
14. A method of fabricating a transistor, the method comprising:
implanting dopant in a first region of a substrate for formation of a drift region in an epitaxial layer of the substrate;
forming a drain region in a second region of the substrate;
wherein the first and second regions laterally overlap to define a conduction path for the transistor, and
wherein the first region does not extend laterally across the second region.
15. The method of claim 14 , further comprising annealing the substrate such that the drift region extends laterally across the second region.
16. The method of claim 15 , wherein annealing the substrate comprises defining a lateral profile of the drift region in which a bottom of the drift region is shallower under the drain region.
17. The method of claim 14 , further comprising, before implanting the dopant for formation of the drift region, forming a field isolation region in the substrate such that the drift region includes a section under the field isolation region.
18. The method of claim 14 , further comprising, after implanting the dopant for formation of the drift region, forming a field isolation region in the substrate such that the drift region includes a section under the field isolation region.
19. The method of claim 14 , further comprising forming the epitaxial layer of the substrate, wherein implanting the dopant in the first region comprises implanting the dopant in the epitaxial layer.
20. The method of claim 14 , further comprising forming a doped buried isolation layer in the substrate that extends across an active area of the transistor to act as a barrier that isolates the transistor from a remainder of the semiconductor substrate.