Granted Patent B2

US 9,804,224 · App. 14/492,633 · Granted Oct 31, 2017

Inventors: Eyal Melamed-Kohen (Modiin, IL); Ilan Cohen (Elad, IL); Shlomi Sde-Paz (Kadima, IL)

Assignee: NXP USA, Inc.

G01R31/31716G01R31/3181

Abstract

Claims (34)

1. An integrated circuit comprising a first functional unit and one or more other functional units, wherein the first functional unit has an input for receiving data and an output for providing data, and wherein the integrated circuit is operable to test the first functional unit and operable to operate the first functional unit normally, and wherein testing the first functional unit comprises:

connecting the input of the first functional unit to the output of the first functional unit, thereby generating a loopback path from the output of the first functional unit to the input of the first functional unit, wherein the loopback path is internal to the first functional unit;

loading a test pattern onto the first functional unit;

feeding a test clock signal comprising one or more clock edges to the first functional unit, thereby prompting the first functional unit to transform the test pattern; and

reading the transformed test pattern from the first functional unit;

wherein operating the first functional unit normally comprises:

connecting the input of the first functional unit to an output of the one or more other functional units; and

feeding a normal clock signal to the first functional unit.

2. The integrated circuit of claim 1 , wherein the first functional unit comprises a logic core having an input connected to the input of the first functional unit and an output connected to the output of the first functional unit.

3. The integrated circuit of claim 2 , wherein loading the test pattern onto the first functional unit comprises loading at least a part of the test pattern onto the logic core.

4. The integrated circuit of claim 1 , comprising a clock arranged to provide both the test clock signal and the normal clock signal.

5. The integrated circuit of claim 1 , wherein the first functional unit comprises one or more multiplexers for connecting the input of the first functional unit either to the output of the first functional unit or to the one or more other functional units in dependence of a mode selection signal.

6. The integrated circuit of claim 1 , wherein the input of the first functional unit is a source-synchronous input and the first functional unit comprises a clock multiplexer for connecting a clock input of the input of the first functional unit either to a clock of the one or more other functional units or to a clock of the first functional unit in dependence of a mode selection signal.

7. The integrated circuit of claim 1 , wherein the input comprises one or more input buffers or wherein the output comprises one or more output buffers.

8. The integrated circuit of claim 7 , wherein loading the test pattern onto the first functional unit comprises loading at least a part of the test pattern onto the input buffers, or onto the output buffers, or onto both the input buffers and the output buffers.

9. The integrated circuit of claim 1 , operable to provide the test pattern or operable to be connected to a host device and to load the test pattern from the host device.

10. The integrated circuit of claim 1 , wherein the integrated circuit is a system-on-chip.

11. The integrated circuit of claim 1 , wherein the first functional unit is an integrated peripheral.

12. A method of operating an integrated circuit, the integrated circuit comprising a first functional unit and one or more other functional units, wherein the first functional unit has an input for receiving data and an output for providing data, and wherein the method comprises testing the first functional unit and operating the first functional unit normally, wherein testing the first functional unit comprises:

connecting the input of the first functional unit to the output of the first functional unit via a multiplexor, thereby providing a loopback path from the output of the first functional unit to the input of the first functional unit, wherein the loopback path is internal to the first functional unit;

loading a test pattern onto the first functional unit;

feeding a test clock signal comprising one or more clock edges to the first functional unit, thereby prompting the first functional unit to transform the test pattern into a transformed pattern; and

reading the transformed pattern from the first functional unit;

and wherein operating the first functional unit normally comprises:

connecting the input of the first functional unit to an output of the one or more other functional units via the multiplexor; and

feeding a normal clock signal to the first functional unit.

13. The method of claim 12 , wherein the first functional unit comprises a logic core and loading the test pattern onto the first functional unit comprises loading at least a part of the test pattern onto the logic core.

14. The method of claim 12 , wherein testing the first functional unit comprises:

connecting the integrated circuit to a host device; and

loading the test pattern from the host device onto the first functional unit.

15. The integrated circuit of claim 10 , wherein the first functional unit is an integrated peripheral.

16. The method of claim 13 , wherein testing the first functional unit comprises:

connecting the integrated circuit to a host device; and

loading the test pattern from the host device onto the first functional unit.

Assignments (15)

Continuity (1)