IP Library Granted Patent US 9,826,630
Granted Patent B2
US 9,826,630 · App. 14/477,729 · Granted Nov 21, 2017

Fan-out wafer level packages having preformed embedded ground plane connections and methods for the fabrication thereof

Inventor: Michael B. Vincent (Chandler, AZ)
Assignee: NXP USA, INC.
H05K1/0298H01L21/78H01L23/552H01L24/19H01L24/96H01L24/97H05K1/0218H05K1/115H05K1/181H05K3/0073H05K3/10H05K3/4644H01L21/561H01L21/568H01L2224/12105H01L2924/19105H05K2201/0715Y10T29/4913
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Quick Facts
Patent No.
US 9,826,630
App. No.
14/477,729
Granted
Nov 21, 2017
Kind
B2
Abstract

Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs having Embedded Ground Plane (EGP) connections are provided. In one embodiment, the method includes forming a molded panel around an EGP array from which a plurality of preformed EGP connections project. One or more Redistribution Layers (RDLs) are produced over the molded panel. The molded panel is then singulated to yield a plurality of FO-WLPs each including a molded package body containing an EGP from the EGP array and one or more of preformed EGP connections.

Claims (34)

1. A method for fabricating Fan-Out Wafer Level Packages (FO-WLPs), comprising:

bonding a plurality of preformed connections to a ground plane array, the ground plane array comprising a plurality of ground plane structures interconnected by a plurality of spars;

after bonding the plurality of preformed connections to the ground plane array, placing the plurality of preformed connections and the ground plane array on a temporary substrate;

after placing the plurality of preformed connections and the ground plane array on the temporary substrate, forming a molded panel over the temporary substrate and around the ground plane array and the plurality of preformed connections to yield an Embedded Ground Plane (EGP) array and a plurality of preformed EGP connections, respectively;

after forming the molded panel, removing material from a backside of the molded panel to thin the molded panel and expose the plurality of preformed EGP connections;

after removing material from the backside of the molded panel, removing the temporary substrate to expose a frontside of the molded panel;

after removing the temporary substrate, producing one or more Redistribution Layers (RDLs) over the frontside of the molded panel; and

after producing the one or more RDLs over the frontside of the molded panel, singulating the molded panel and severing the ground plane array through the plurality of spars to yield a plurality of FO-WLPs, each of the plurality of FO-WLPs including a molded package body containing a singulated EGP separated from the EGP array and one or more of the preformed EGP connections.

2. The method of claim 1 further comprising providing an Electromagnetic Interference (EMI) shield on the backside of the molded package body and electrically coupled to the singulated EGP through the one or more preformed EGP connections.

3. The method of claim 1 further comprising depositing at least one continuous electrically-conductive layer over the backside of the molded panel and in ohmic contact with the plurality of preformed EGP connections, the at least one continuous electrically-conductive layer forming Electromagnetic Interference (EMI) shields included within the plurality of FO-WLPs when the molded panel is singulated.

4. The method of claim 1 wherein bonding the plurality of preformed ground plane connections to the ground plane array, comprises:

dispensing an electrically-conductive material in a predetermined pattern over the ground plane array; and

curing the electrically-conductive material to produce the plurality of preformed connections.

5. The method of claim 4 wherein dispensing comprises:

positioning a stencil over the ground plane array, the stencil having stencil openings defining a shape and position of the plurality of preformed connections; and

applying the electrically-conductive material into the stencil openings and onto the ground plane array.

6. The method of claim 4 wherein the electrically-conductive material comprises a metal particle-filled adhesive, and wherein the curing comprises sintering the metal particle-filled adhesive to produce the plurality of preformed connections.

7. The method of claim 1 wherein the plurality of preformed connections comprise a plurality of electrically-conductive structures, and wherein bonding comprises bonding the plurality of electrically-conductive structures to the ground plane array utilizing an electrically-conductive adhesive prior to forming the molded panel.

8. The method of claim 1 wherein forming comprises forming the molded panel around the ground plane array, the plurality of preformed connections, and a plurality of electrical components positioned in openings provided in the ground plane array.

9. The method of claim 8 wherein the plurality of preformed connections comprise substantially continuous walls extending around the openings provided in the ground plane array and a semiconductor die positioned therein.

10. The method of claim 9 further comprising:

positioning the electrical components in the openings and surrounded by the substantially continuous walls, wherein the electrical components are selected from semiconductor die and discrete components, and wherein at least some of the electrical components are configured to operate at radio frequencies (RF); and

forming at least one Electromagnetic Interference (EMI) shield on the backside of the molded package body cooperating with the substantially continuous walls to form an EMI cage enclosing the electrical components.

11. The method of claim 1 further comprising producing the plurality of preformed connections as a plurality of vertically-extending columns projecting upwardly from selected locations of the ground plane array.

12. The method of claim 1 wherein bonding comprises:

aligning a stencil with the ground plane array;

after aligning the stencil to the ground plane array, utilizing a squeegee to applying an electrically-conductive material over the stencil and into openings provided in the stencil;

curing the electrically-conductive material to form the plurality of preformed connections; and

after curing, removing the stencil from over the ground plane array.

13. The method of claim 1 wherein removing material comprises thinning the backside of the molded panel to expose portions of the plurality of preformed EGP connections, while imparting the backside with a substantially planar geometry; and

wherein the method further comprises, after thinning, forming an Electromagnetic Interference (EMI) shield on the backside of the molded package body and in electrical contact with the exposed portions of the plurality of preformed EGP connections.

14. The method of claim 1 further comprising:

selecting the plurality of ground plane structures to comprise rectangular bodies; and

forming the plurality of preformed connections to comprise continuous walls extending over and around the rectangular bodies of the plurality of ground plane structures.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0502 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0460 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0921 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034153/0027 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0351 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0370 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2014
From: VINCENT, MICHAEL B.
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 033672/0721 →
Continuity (1)
Related Publication 20160073496A1 · Mar 10, 2016