Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor
A method of making a split gate non-volatile memory (NVM) using a substrate includes etching a recess into an isolation region of an NVM region of the substrate and depositing a conductive layer and a capping layer. A select gate and a control gate are formed in the NVM region, and a dummy gate is formed in a logic region of the substrate. A portion of the capping layer is removed and a salicide block bi-layer is deposited and patterned to form a first opening that exposes a contact portion of the conductive layer over the recess. A silicided region is formed on the contact portion. The substrate is planarized to expose the dummy gate, which is replaced with a metal gate. A second opening is etched through a first interlayer dielectric deposited over the substrate to the silicided region. Contact metal is deposited into the second opening.
1. A method of making a semiconductor structure using a substrate, wherein the semiconductor structure comprises a split gate non-volatile memory (NVM) cell in an NVM region of the substrate, the method comprising:
etching a recess into an isolation region of the substrate in the NVM region;
depositing a polysilicon layer over the substrate, including over the recess;
depositing a nitride layer over the polysilicon layer;
forming a polysilicon select gate and a polysilicon control gate in the NVM region;
forming a polysilicon gate in a logic region of the substrate;
removing a portion of the nitride layer over the recess;
depositing a salicide block bi-layer over the substrate, including over the recess;
patterning the salicide block bi-layer to form a first opening in the salicide block bi-layer that exposes a contact portion of the polysilicon layer over the recess;
forming a silicided region on the contact portion of the polysilicon layer over the recess within the first opening;
planarizing the substrate to expose the polysilicon gate;
replacing the polysilicon gate with a metal gate;
depositing a first interlayer dielectric over the substrate;
etching a second opening through the first interlayer dielectric to the silicided region; and
depositing contact metal into the second opening.
2. The method of claim 1 , further comprising:
forming an oxide layer over the polysilicon layer before the depositing the nitride layer over the polysilicon layer.
3. The method of claim 1 , further comprising:
forming a hard mask over the NVM region, including over the polysilicon select gate and the polysilicon control gate, subsequent to the forming the polysilicon select gate and the polysilicon control gate in the NVM region.
4. The method of claim 3 , wherein the forming the polysilicon gate in the logic region further comprises:
forming a dummy stack that includes the polysilicon gate in the logic region of the substrate, subsequent to the forming the hard mask over the NVM region.
5. The method of claim 4 , further comprising:
forming sidewall spacers and source/drain regions around the dummy stack that includes the polysilicon gate, the polysilicon select gate, and the polysilicon control gate.
6. The method of claim 1 , wherein
the contact metal comprises one or more metal layers.
7. The method of claim 1 , wherein the patterning the salicide block bi-layer further comprises:
forming a photoresist over the salicide block bi-layer, the photoresist having the first opening that exposes the contact portion of the polysilicon layer over the recess; and
removing the salicide block bi-layer that is not under the photoresist to expose the nitride layer outside of the recess and the contact portion of the polysilicon layer over the recess.
8. The method of claim 1 , further comprising:
depositing a second interlayer dielectric over the substrate, including over the recess, subsequent to the forming the silicided region.
9. The method of claim 8 , wherein
the second interlayer dielectric comprises a second nitride layer over the silicided region, and
the second nitride layer provides an etch stop during the planarizing the substrate.
10. The method of claim 8 , further comprising:
forming an oxide layer over the substrate in the NVM region, subsequent to the planarizing the substrate.
11. The method of claim 10 , wherein
a remaining portion of the second interlayer dielectric remains over the silicided region subsequent to the planarizing the substrate, and
the oxide layer is formed over the substrate, including over the remaining portion of the second interlayer dielectric.
12. The method of claim 11 , wherein the etching the second opening further comprises:
etching the second opening through the first interlayer dielectric, the oxide layer, and the remaining portion of the second interlayer dielectric to the silicided region.
13. The method of claim 1 , wherein
the salicide block bi-layer comprises an oxide-nitride layer.
14. The method of claim 4 , wherein
the dummy stack includes a high-k dielectric layer.
15. A method of making a semiconductor structure using a substrate, wherein the semiconductor structure comprises a split gate non-volatile memory (NVM) cell in an NVM region of the substrate, the method comprising:
etching a recess into an isolation region of the substrate in the NVM region;
depositing a conductive layer over the substrate, including over the recess;
depositing a capping layer over the conductive layer;
forming a select gate and a control gate in the NVM region, the select gate and the control gate each including a portion of the conductive layer;
forming a dummy gate in a logic region of the substrate;
removing a portion of the capping layer over the recess;
depositing a salicide block bi-layer over the substrate, including over the recess;
patterning the salicide block bi-layer to form a first opening in the salicide block bi-layer that exposes a contact portion of the conductive layer over the recess;
forming a silicided region on the contact portion of the conductive layer over the recess within the first opening;
planarizing the substrate to expose the dummy gate;
replacing the dummy gate with a metal gate;
depositing a first interlayer dielectric over the substrate;
etching a second opening through the first interlayer dielectric to the silicided region; and
depositing contact metal into the second opening.
16. The method of claim 15 , wherein
during the forming the dummy gate, a high-k dielectric layer is formed under the dummy gate,
the high-k dielectric layer remains under the metal gate subsequent to the replacing the dummy gate with the metal gate, and
the metal gate comprises one or more metal layers.
17. The method of claim 15 , wherein
the contact metal comprises one or more metal layers.
18. A semiconductor structure using a substrate having a non-volatile memory (NVM) region and a logic region, comprising:
a split gate NVM cell in the NVM region, the split gate NVM cell comprising:
a polysilicon select gate, and
a polysilicon control gate;
a contact electrode in an isolation region of the substrate in the NVM region, the contact electrode being over a recess into the isolation region, the contact electrode comprising a silicided region on a contact portion of a polysilicon layer over the recess; and
a metal gate stack in the logic region.
19. The semiconductor structure of claim 18 , wherein
the metal gate stack includes a high-k dielectric layer over the substrate and one or more metal layers.
20. The semiconductor structure of claim 18 , wherein
the contact electrode further includes contact metal that comprises one or more metal layers.