IP Library Granted Patent US 9,553,184
Granted Patent B2
US 9,553,184 · App. 14/473,358 · Granted Jan 24, 2017

Edge termination for trench gate FET

Inventors: Moaniss Zitouni (Gilbert, AZ); Edouard de Frésart (Tempe, AZ); Pon Sung Ku (Gilbert, AZ); Ganming Qin (Chandler, AZ)
Assignee: NXP USA, INC.
H01L29/7811H01L21/26513H01L21/76897H01L29/063H01L29/0696H01L29/4236H01L29/66666H01L29/66734H01L29/7813
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Quick Facts
Patent No.
US 9,553,184
App. No.
14/473,358
Granted
Jan 24, 2017
Kind
B2
Abstract

A semiconductor device includes a semiconductor layer disposed at a substrate and a plurality of active cells disposed at the semiconductor layer. Each active cell includes a trench extending into the semiconductor layer and a body region disposed in the semiconductor layer adjacent to a sidewall of the trench and at a first depth below the surface of the semiconductor layer. The semiconductor device further includes a termination cell disposed at the semiconductor layer adjacent to an edge of the plurality of active cells. The termination cell includes a trench extending into the semiconductor layer, and further includes a body region disposed in the semiconductor layer adjacent to a sidewall of the trench of the termination cell and at a second depth less than the first depth. The body regions of the active cells and of the termination cell have a conductivity type different than that of the semiconductor layer.

Claims (67)

1. A semiconductor device comprising:

a semiconductor layer disposed at a substrate of the semiconductor device, the semiconductor layer having a first conductivity type;

a plurality of active cells disposed at the semiconductor layer, each active cell comprising:

a trench extending into the semiconductor layer from a surface of the semiconductor layer;

a body region disposed in the semiconductor layer adjacent to a sidewall of the trench of the active cell and at a first depth below the surface such that the entirety of the body region is separated from the surface by a directly interposing region of the semiconductor layer, the body region of the active cell having a second conductivity type different than the first conductivity type; and

a first body contact region extending from the body region of the active cell to the surface of the semiconductor layer, and

a termination cell disposed at the semiconductor layer adjacent to an edge of the plurality of active cells, the termination cell comprising:

a trench extending into the semiconductor layer from the surface of the semiconductor layer;

a body region disposed in the semiconductor layer adjacent to a sidewall of the trench of the termination cell and at a second depth less than the first depth, the body region of the termination cell having the second conductivity type; and

a second body contact region extending from the body region of the termination cell to the surface of the semiconductor layer; and

wherein the body region of the termination cell extends from the second depth to a third depth at its lowermost depth, and the body regions of the active cells extend from the first depth to a fourth depth at their lowermost depths, the fourth depth greater than the third depth.

2. The semiconductor device of claim 1 , wherein the second depth is at the surface.

3. The semiconductor device of claim 1 , further comprising:

a segment of a shield electrode disposed in the trench of the termination cell.

4. The semiconductor device of claim 3 , further comprising:

corresponding segments of the shield electrode disposed underneath gate electrodes in the trenches of the active cells.

5. The semiconductor device of claim 1 , wherein the semiconductor device further comprises:

conductive plugs contacting the first and second body contact regions; and

a body electrode contacting the conductive plugs.

6. A method for forming a semiconductor device, the method comprising:

providing a semiconductor layer overlying a substrate, the semiconductor layer having a first conductivity type;

forming, for each active cell of a plurality of active cells, a trench extending into the semiconductor layer from a surface of the semiconductor layer;

forming, for a termination cell at a periphery of the plurality of active cells, a trench adjacent to at least one edge of the plurality of active cells at the semiconductor layer, the trench extending into the semiconductor layer from the surface of the semiconductor layer;

forming, for each active cell of the plurality of active cells, a first body region at a first depth below the surface in the semiconductor layer and adjacent to a sidewall of the trench of the active cell such that the entirety of the first body region is separated from the surface by a directly interposing region of the semiconductor layer, the first body region having a second conductivity type different than the first conductivity type;

forming, for each active cell of the plurality of cells, a first body contact region extending from the first body region of the active cell to the surface of the semiconductor layer;

forming, for the termination cell, a second body region at a second depth in the semiconductor layer adjacent to a sidewall of the trench of the termination cell, the second body region having the second conductivity type and the second depth being less than the first dept;

forming, for the termination cell, a second body contact region extending from the second body region of the termination cell to the surface of the semiconductor layer; and

wherein the second body region of the termination cell extends from the second depth to a third depth at its lowermost depth, and the first body region of the cells extend from the first depth to a fourth depth at their lowermost depths, the fourth depth greater than the third depth.

7. The method of claim 6 , wherein:

forming the first body region comprises performing a first ion implant process at a first implant energy level; and

forming the second body region comprises performing a second ion implant process at a second implant energy level lower than the first implant energy level.

8. The method of claim 7 , wherein:

forming the first body region comprises implementing a first mask during the first ion implant process to prevent ion implantation in the second body region during the first ion implant process; and

forming the second body region comprises implementing a second mask during the second ion implant process to prevent ion implantation in the first body region of each of the active cells during the second ion implant process.

9. The method of claim 7 , wherein:

performing the first ion implant process comprises performing a P-type implant process at an implant energy in a range of approximately 700 to 900 kilo-electron-volts; and

performing the second ion implant process comprises performing a P-type implant process at an implant energy in a range of approximately 400 to 600 kilo-electron-volts.

10. The method of claim 7 , wherein:

forming the first body contact region comprises forming the first body contact region using a chained ion implant process, the chained ion implant process comprising a series of ion implant processes at different implant energies; and

forming the second body contact region comprises forming the second body contact region using the chained ion implant process.

11. The method of claim 10 , further comprising:

forming, for each active cell, a first conductive plug contacting the first body contact region of the active cell;

forming a second conductive plug contacting the second body contact region of the termination cell; and

forming a body electrode contacting the first and second conductive plugs.

12. The method of claim 6 , wherein:

forming the first body region comprises performing a single ion implant process at a first implant energy level; and

forming the second body region comprises performing a chained ion implant process that uses a series of ion implant processes at different implant energies.

13. The method of claim 12 , wherein the ion implant process at the first implant energy level is one of the ion implant processes of the chain ion implant process.

14. The method of claim 12 , wherein forming the second body region comprises forming the second body region at a non-zero depth below the surface of the semiconductor layer.

15. The method of claim 12 , further comprising:

forming, for each active cell, a conductive plug contacting the first body contact region of the active cell; and

forming a body electrode contacting the conductive plug.

16. The method of claim 6 , wherein:

forming the trench of each active cell comprises forming a corresponding segment of a shield electrode in the trench of the active cell; and

forming the trench of the termination cell comprises forming a corresponding segment of the shield electrode in the trench of the termination cell.

17. The method of claim 6 , wherein providing the semiconductor layer overlying the substrate comprises epitaxially growing the semiconductor layer on the substrate.

18. The method of claim 6 , wherein the second depth is at the surface of the semiconductor layer.

19. A semiconductor device comprising:

an active cell comprising:

a first trench extending into a semiconductor layer of the semiconductor device, the first trench comprising a segment of a gate electrode overlying a segment of a shield electrode; and

a first body region disposed below a surface of the semiconductor layer and adjacent to the first trench such that the entirety of the first body region is separated from the surface by a directly interposing region of the semiconductor layer, the first body region extending, at its greatest extent, to a first depth below the surface of the semiconductor layer and having a conductivity type different than a conductivity type of the semiconductor layer; and

a first body contact region extending from the body region of the active cell to the surface of the semiconductor layer; and

a termination cell disposed at the semiconductor layer adjacent to the active cell, the termination cell comprising:

a second trench extending into the semiconductor layer of the semiconductor device, the second trench comprising a segment of the gate electrode overlying a segment of the shield electrode;

a second body region disposed adjacent to the second trench, the second body region extending from the surface of the semiconductor layer to a second depth below the surface of the semiconductor layer that is less than the first depth, and the second body region having a conductivity type different than the conductivity type of the semiconductor layer; and

a second body contact region extending form the first body region of the active cell to the surface if the semiconductor layer, and

wherein the second body region of the termination cell extends from the second depth to a third depth at its greatest extent, and the first body region of the active cells extends from the first depth to a fourth depth at its greatest extent, the fourth depth greater than the third depth.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTATION - INITIAL CONVENYANCE LISTED CHANGE OF NAME. PREVIOUSLY RECORDED ON REEL 040579 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE UPDATE CONVEYANCE TO MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Dec 15, 2016
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 040945/0252 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
CHANGE OF NAME Recorded Nov 9, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040579/0827 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0460 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0502 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0921 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0370 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0351 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034153/0027 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2014
From: DE FRESART, EDOUARD; ZITOUNI, MOANISS; QIN, GANMING; KU, PON SUNG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 033649/0183 →
Continuity (1)
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