Method and apparatus for detecting a state of an alternator regulator
A detection circuit for an alternator regulator, and method therefor. The detection circuit comprises an input circuit arranged to receive a phase signal from an alternator regulator and to output an attenuated sense signal representative of the received phase signal, a detection component operably coupled to the input circuit and arranged to receive the attenuated sense signal output by the input circuit, and a blocking capacitance operably coupled between the input circuit and the detection component and arranged to block a DC component of the attenuated sense signal. The detection component is arranged to compare the received attenuated sense signal to at least one reference voltage signal, and to output a signal representative of a frequency of the phase signal from the alternator regulator based at least partly on the comparison of the received attenuated sense signal to the at least one reference voltage signal.
1. A detection circuit for an alternator regulator, the detection circuit comprising:
an input circuit arranged to receive a phase signal from the alternator regulator and to output an attenuated sense signal representative of the received phase signal;
a detection component operably coupled to the input circuit and arranged to receive the attenuated sense signal output by the input circuit; and
a blocking capacitance operably coupled between the input circuit and the detection component and arranged to block a DC component of the attenuated sense signal,
wherein the detection component is arranged to compare the received attenuated sense signal to at least one reference voltage signal, and to output a signal representative of a frequency of the phase signal from the alternator regulator based at least partly on the comparison of the received attenuated sense signal to the at least one reference voltage signal.
2. The detection circuit of claim 1 , wherein the input circuit comprises a high input impedance.
3. The detection circuit of claim 2 , wherein the input circuit comprises a high impedance voltage divider circuit.
4. The detection circuit of claim 1 , wherein the input circuit comprises an input clamp component arranged to clamp the attenuated sense signal to within a maximum voltage level.
5. The detection circuit of claim 4 , wherein the input clamp component is arranged to clamp the attenuated sense signal to a maximum modulus voltage level.
6. The detection circuit of claim 1 , wherein the input circuit comprises a low pass filter component arranged to apply low pass filtering to the attenuated sense signal output thereby.
7. The detection circuit of claim 1 , wherein the detection component is arranged to apply a bias voltage to the received attenuated sense signal, and to compare the biased attenuated sense signal to the at least one reference voltage signal derived from the bias voltage.
8. The detection circuit of claim 7 , wherein the detection component comprises a set-reset flip-flop arranged to receive at inputs thereof the first and second comparison signals, and to output the signal representative of the frequency of the phase signal from the alternator regulator.
9. The detection circuit of claim 8 , wherein the first offset reference voltage signal comprises a voltage greater than a bias voltage Vref by a reference voltage difference ΔVth and the second offset reference voltage signal comprises a voltage less than the bias voltage Vref by the reference voltage difference ΔVth, such that the first offset reference voltage signal is equal to Vref+ΔVth and the second offset reference voltage signal is equal to Vref−ΔVth.
10. The detection circuit of claim 8 , wherein the detection component comprises a voltage divider circuit operably coupled between a high voltage node and a low voltage node; the voltage divider circuit comprising:
a first node arranged to provide the bias voltage Vref;
a second node operably coupled to the first node via a first resistance and to the high voltage node and arranged to provide the first offset reference voltage; and
a third node operably coupled to the first node via a second resistance and to the low voltage node and arranged to provide the second offset reference voltage.
11. The detection circuit of claim 1 , wherein the detection component comprises a comparison circuit arranged to:
compare the received attenuated sense signal to a first offset reference voltage signal, and to output a first comparison signal based on the comparison of the attenuated sense signal to the first offset reference voltage signal; and
compare the received attenuated sense signal to a second offset reference voltage signal, and to output a second comparison signal based on the comparison of the attenuated sense signal to the second offset reference voltage signal,
wherein the detection component is arranged to output the signal representative of the frequency of the phase signal from the alternator regulator based at least partly on the first and second comparison signals.
12. The detection circuit of claim 11 , wherein the first offset reference voltage signal comprises a voltage greater than a bias voltage Vref by a reference voltage difference ΔVth and the second offset reference voltage signal comprises a voltage less than the bias voltage Vref by the reference voltage difference ΔVth, such that the first offset reference voltage signal is equal to Vref+ΔVth and the second offset reference voltage signal is equal to Vref−ΔVth.
13. The detection circuit of claim 12 , wherein the detection component comprises a sense clamp component arranged to clamp the attenuated sense signal received thereby to within a sense clamp voltage difference ΔVsns of the bias voltage Vref, such that the sense signal is clamped to within ±ΔVsns of the bias voltage Vref.
14. The detection circuit of claim 12 , wherein the detection component comprises a voltage divider circuit operably coupled between a high voltage node and a low voltage node; the voltage divider circuit comprising:
a first node arranged to provide the bias voltage Vref;
a second node operably coupled to the first node via a first resistance and to the high voltage node and arranged to provide the first offset reference voltage; and
a third node operably coupled to the first node via a second resistance and to the low voltage node and arranged to provide the second offset reference voltage.
15. The detection circuit of claim 11 , wherein the detection component comprises a voltage divider circuit operably coupled between a high voltage node and a low voltage node; the voltage divider circuit comprising:
a first node arranged to provide the bias voltage Vref;
a second node operably coupled to the first node via a first resistance and to the high voltage node and arranged to provide the first offset reference voltage; and
a third node operably coupled to the first node via a second resistance and to the low voltage node and arranged to provide the second offset reference voltage.
16. The detection circuit of claim 15 , wherein the sense clamp voltage difference ΔVsns is greater than the reference voltage difference ΔVth.
17. The detection circuit of claim 15 , wherein the sense clamp component comprises two diode structures operably coupled in parallel between the input of the detection component at which the attenuated sense signal is received and a source node of the bias voltage Vref, and facing in opposite directions.
18. The detection circuit of claim 15 , wherein the detection component comprises a sense clamp component arranged to clamp the attenuated sense signal received thereby to within a sense clamp voltage difference ΔVsns of the bias voltage Vref, such that the sense signal is clamped to within ±ΔVsns of the bias voltage Vref.
19. The detection circuit of claim 1 implemented within an integrated circuit device comprising at least one die within a single integrated circuit package.
20. A method of detecting a state of an alternator regulator, the method comprising:
receiving a phase signal from the alternator regulator;
attenuating the received phase signal to produce an attenuated sense signal representative of the received phase signal;
blocking a DC component of the attenuated sense signal;
comparing the attenuated sense signal to at least one reference voltage signal; and
generating a signal representative of a frequency of the received phase signal based at least partly on the comparison of the received attenuated sense signal to the at least one reference signal.