Granted Patent B1

US 9,191,021 · App. 14/696,482 · Granted Nov 17, 2015

Abstract

Claims (87)

1. A pipelined analog-to-digital converter (ADC) that converts an analog input voltage signal V in into a digital output value D out , the ADC comprising a sequence of stages including at least a first calibrated stage comprising:

an ADC sub-module that receives the analog input voltage signal V in and provides an ADC sub-module digital output value based on the analog input voltage signal V in ;

a digital-to-analog converter (DAC) sub-module that receives the ADC sub-module digital output value and outputs a corresponding analog voltage signal V DAC ;

a first difference module that generates an analog residual voltage signal based on a difference between the analog input voltage signal V in and the analog voltage signal V DAC ; and

an artificial-noise-insertion module that inserts an analog artificial-noise voltage signal into the residual voltage signal to generate an analog combined voltage signal,

wherein:

the analog combined voltage signal can be used to calibrate the first calibrated stage; and

the artificial-noise-insertion module generates the polarity of the artificial-noise voltage signal based on the polarity of the corresponding residual voltage signal.

2. The ADC of claim 1 , wherein:

the first calibrated stage further comprises an amplifier having a nominal gain G, wherein the amplifier amplifies the combined voltage signal to generate an amplified voltage signal;

the amplified voltage signal is output from the first calibrated stage and provided to the next stage of the sequence of stages; and

the amplifier has an actual gain that is a product of (1) the nominal gain G and (2) 1+e, where e is an error factor.

3. The ADC of claim 1 , wherein:

the ADC sub-module comprises a first plurality of comparators having corresponding outputs;

the first calibrated stage further comprises:

a comparator module comprising a second plurality of comparators, each comparator connected to receive the analog input voltage signal V in and provide a corresponding output value; and

an encoder that:

receives (1) the output values of the first plurality of comparators in the ADC sub-module and (2) the output values of the second plurality of comparators in the comparator module; and

provides an encoder output value based on the output values received from the first and second pluralities of comparators.

4. The ADC of claim 3 , wherein:

reference voltage V ref is a maximum expected voltage for the analog input voltage signal V in ;

the first plurality of comparators compare the analog input voltage signal V in to −V ref /4 and V ref /4; and

the second plurality of comparators compare the analog input voltage signal V in to −V ref /2, 0, and V ref /2.

5. The ADC of claim 3 , wherein the encoder output value indicates the polarity of the residual voltage signal.

6. The ADC of claim 3 , wherein:

the ADC sub-module has a resolution r; and

the number of comparators c in the comparator module is c=2^(r+0.5)−1.

7. The ADC of claim 3 , wherein the artificial-noise-insertion module comprises:

a random-number (RN) generator that:

receives the encoder output value;

generates a random-like sequence of values; and

generates an RN-generator output value based on a corresponding value of the random-like sequence of values and the encoder output value;

a calibration DAC that generates the analog artificial-noise voltage signal based on the RN-generator output value and a scalar voltage level S; and

a combining module that inserts the analog artificial-noise voltage signal into the residual voltage signal to generate the combined voltage signal.

8. The ADC of claim 7 , wherein:

each value of the random-like sequence of values generated by the RN generator is used to determine an alternating two-value sequence of desired polarities for a product of the values of (1) the received encoder output and (2) the output of the RN generator; and

the RN-generator output value is generated to achieve the corresponding desired polarity for the product of the values of (1) the corresponding received encoder output and (2) the RN-generator output value.

9. The ADC of claim 8 , wherein:

if a value of the random-like sequence of values is zero, then the corresponding alternating two-value sequence of desired polarities is positive and then negative; and

if a value of the random-like sequence of values is one, then the corresponding alternative two-value sequence of desired polarities is negative and then positive.

10. The ADC of claim 8 , wherein:

if a value of the random-like sequence of values is zero, then the corresponding alternating two-value sequence of desired polarities is negative and then positive; and

if a value of the random-like sequence of values is one, then the corresponding alternative two-value sequence of desired polarities is positive and then negative.

11. The ADC of claim 8 , wherein:

if the desired polarity is positive and the corresponding encoder output value has a positive polarity, then the output value of the RN generator has a positive polarity;

if the desired polarity is positive and the corresponding encoder output value has a negative polarity, then the output value of the RN generator has a negative polarity;

if the desired polarity is negative and the corresponding encoder output value has a positive polarity, then the output value of the RN generator has a negative polarity; and

if the desired polarity is negative and the corresponding encoder output value has a negative polarity, then the output of the RN generator has a positive polarity.

12. The ADC of claim 1 , further comprising a calibration and summation module adapted to:

receive the ADC sub-module output value as a first-stage output value;

receive one or more other-stage output values from the one or more other stages of the sequence;

process the first stage output value and the one or more other-stage output values to (1) determine gain error for the first calibrated stage and (2) cancel the inserted artificial-noise voltage signal.

13. The ADC of claim 12 , wherein:

the sequence of stages comprises N consecutive stages;

the first-stage output value is delayed in the calibration and summation module by N−1 clock cycles;

each of the one or more other-stage output values is delayed in the calibration and summation module by up to N−2 clock cycles.

14. The ADC of claim 13 , wherein the calibration and summation module comprises, for the first calibrated stage:

a first calibration circuit that (a) receives (1) a summation value corresponding to the one or more other stages and (2) a scalar value, (b) performs the determination of error parameters for the first calibrated stage and cancellation of the inserted artificial-noise voltage signal, and (c) generates a calibration-circuit output value;

an amplifier that receives the calibration-circuit output value and output a modulated calibration-circuit output value; and

a summation module that combines the modulated calibration-circuit output value with the delayed first-stage output value to generate the digital output value D out .

15. The ADC of claim 1 , wherein the sequence of stages includes a second calibrated stage, wherein the second calibrated stage is calibrated before the first calibrated stage is calibrated.

16. A method for calibrating a pipelined analog-to-digital converter (ADC) that converts an analog input voltage signal V in into a digital output value D out and comprises a sequence of stages including at least a first calibrated stage comprising an ADC sub-module, a digital-to-analog converter (DAC) sub-module, a first difference module, and an artificial-noise-insertion module, the method comprising:

receiving, by the ADC sub-module, the analog input voltage signal V in and providing an sub-module digital output value based on the analog input voltage signal V in ;

receiving, by the digital-to-analog converter (DAC) sub-module, the ADC sub-module digital output value and outputting a corresponding analog voltage signal V DAC ;

generating, by the first difference module, an analog residual voltage signal based on a difference between the analog input voltage signal V in and the analog voltage signal V DAC ; and

inserting, by the artificial-noise-insertion module, an analog artificial-noise voltage signal into the residual voltage signal to generate an analog combined voltage signal, wherein:

the analog combined voltage signal is used to calibrate the first calibrated stage; and

the artificial-noise-insertion module generates the polarity of the artificial-noise voltage signal based on the polarity of the corresponding residual voltage signal.

17. The method of claim 16 , further comprising:

amplifying, by an amplifier having a nominal gain G, the combined voltage signal to generate an amplified voltage signal, wherein the actual gain of the amplifier is the product of (1) the nominal gain G and (2) 1+e, where e is an error factor; and

outputting, by the first calibrated stage, the amplified voltage signal for provision to the next stage of the sequence of stages.

18. The method of claim 16 , wherein:

the ADC sub-module comprises a first plurality of comparators having corresponding outputs;

the first calibrated stage further comprises:

a comparator module comprising a second plurality of comparators, each comparator adapted to receive the analog input voltage signal V in and provide a corresponding output value; and

an encoder; and

the method further comprises:

receiving, by the encoder, (1) the output values of the first plurality of comparators from the ADC sub-module and (2) the output values of the second plurality of comparators from the comparator module; and

providing, by the encoder, an encoder output value based on the output values received from the first and second pluralities of comparators.

19. The method of claim 18 , wherein the encoder output value indicates the polarity of the first residual voltage signal.

20. The method of claim 18 , wherein:

the artificial-noise-insertion module comprises a random-number (RN) generator, a calibration DAC, and a combining module; and

the method further comprises:

receiving, by the RN generator, the encoder output value, and generating a random-like sequence of values;

generating, by the RN generator, an RN generator output value based on a corresponding value of the random-like sequence of values and the encoder output value;

generating, by the calibration DAC, the analog artificial-noise voltage signal based on the RN-generator output value and a scalar voltage level S; and

inserting, by the combining module, the analog artificial-noise voltage signal into the residual-voltage signal to generate the combined voltage signal.

Assignments (15)