Patent Assignment
Reel/Frame 036284/0363
SUPPLEMENT TO IP SECURITY AGREEMENT
Recorded: 2015-08-06
Received: 2015-08-06
Pages: 17
Assignor
FREESCALE SEMICONDUCTOR, INC.
Executed: 2015-07-24
Assignee
CITIBANK, N.A., AS NOTES COLLATERAL AGENT
390 GREENWICH STREET, NEW YORK, NY, 10013, UNITED STATES
Covered Applications
(100)
APPARATUS AND METHOD FOR MONITORING ELECTRICAL CURRENT
App. No. 14/766,762
→
INTEGRATED CIRCUIT WITH MULTIPLEXED I/O PADS
App. No. 14/821,776
→
FLASH MEMORY CONTROLLER, DATA PROCESSING SYSTEM WITH FLASH MEMORY CONTROLLER AND METHOD OF OPERATING A FLASH MEMORY CONTROLLER
App. No. 14/755,010
→
ELECTRONIC DEVICE WITH DEMONSTRATION MODE
App. No. 14/788,401
→
INHIBITING PROPAGATION OF SURFACE CRACKS IN A MEMS DEVICE
App. No. 14/755,595
→
NON-VOLATILE DYNAMIC RANDOM ACCESS MEMORY (NVDRAM)
App. No. 14/788,285
→
NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM)
App. No. 14/788,273
→
SYNCHRONOUS COMMUNICATION BETWEEN SYSTEM IN PACKAGE (SIP) DEVICES
App. No. 14/788,363
→
RING OSCILLATOR CIRCUIT AND METHOD OF REGULATING AGGREGATE CHARGE STORED WITHIN CAPACITIVE LOADING THEREFOR
App. No. 14/755,119
→
WAFER-LEVEL MAGNETIC FIELD PROGRAMMING OF MAGNETIC FIELD SENSORS
App. No. 14/754,075
→
LOW INTERFERENCE CELLULAR DATA COMMNUNICATION IN UNLICENSED FREQUENCY SPECTRUM
App. No. 14/753,730
→
MAGNETIC FIELD PROGRAMMING OF ELECTRONIC DEVICES ON A WAFER
App. No. 14/754,069
→
PIPELINED DECODER AND METHOD FOR CONDITIONAL STORAGE
App. No. 14/753,136
→
Systems And Methods For Asymmetric Memory Access To Memory Banks Within Integrated Circuit Systems
App. No. 14/753,153
→
ADAPTIVE HIGH-ORDER NONLINEAR FUNCTION APPROXIMATION USING TIME-DOMAIN VOLTERRA SERIES TO PROVIDE FLEXIBLE HIGH PERFORMANCE DIGITAL PRE-DISTORTION
App. No. 14/752,574
→
HIGH SPEED GALLIUM NITRIDE TRANSISTOR DEVICES
App. No. 14/752,066
→
DOUBLE INTEGRATOR PULSE WAVE SHAPER APPARATUS, SYSTEM AND METHOD
App. No. 14/752,613
→
METHOD FOR TESTING ANALOG-TO-DIGITAL CONVERTER AND SYSTEM THEREFOR
App. No. 14/751,804
→
IC MODULE AND METHOD OF DECODING RESOURCE ACCESS REQUESTS
App. No. 14/752,216
→
SYSTEMS AND METHODS TO DYNAMICALLY CALIBRATE AND ADJUST GAINS IN A DIRECT CONVERSION RECEIVER
App. No. 14/749,884
→
METHOD AND APPARATUS FOR SECURE RECORDATION OF TIME OF ATTEMPTED BREACH OF IC PACKAGE
App. No. 14/749,749
→
A METHOD AND APPARATUS FOR USING A CPU CACHE MEMORY FOR NON-CPU RELATED TASKS
App. No. 14/655,109
→
ELECTRONIC HIGH FREQUENCY DEVICE AND MANUFACTURING METHOD
App. No. 14/655,134
→
APPARATUS AND METHODS FOR STACKABLE PACKAGING
App. No. 14/749,243
→
INTEGRATED CIRCUIT PROCESSOR AND METHOD OF OPERATING THE INTEGRATED CIRCUIT PROCESSOR IN DIFFERENT MODES OF DIFFERING THREAD COUNTS
App. No. 14/655,122
→
ELECTRONIC DEVICE AND METHOD FOR STATE RETENTION
App. No. 14/655,057
→
METHOD AND CONTROL DEVICE FOR RECOVERING NBTI/PBTI RELATED PARAMETER DEGRADATION IN MOSFET DEVICES
App. No. 14/655,150
→
A METHOD AND APPARATUS FOR ADAPTIVE GRAPHICS COMPRESSION AND DISPLAY BUFFER SWITCHING
App. No. 14/655,183
→
A HOMOGENEITY DETECTION CIRCUIT, A VALVE DRIVING SYSTEM AND A METHOD OF HOMOGENEITY DETECTION IN A VALVE DRIVING SYSTEM
App. No. 14/655,213
→
PACKET PROCESSING ARCHITECTURE AND METHOD THEREFOR
App. No. 14/655,168
→
APPARATUS AND METHOD FOR VERIFYING IMAGE DATA COMPRISING MAPPED TEXTURE IMAGE DATA
App. No. 14/746,980
→
SEMICONDUCTOR DEVICES AND METHODS FOR DEAD TIME OPTIMIZATION BY MEASURING GATE DRIVER RESPONSE TIME
App. No. 14/747,981
→
APPARATUS AND METHOD FOR VERIFYING THE ORIGIN OF TEXTURE MAP IN GRAPHICS PIPELINE PROCESSING
App. No. 14/747,023
→
INTEGRATED CIRCUIT INCLUDING OVERLAPPING SCAN DOMAINS
App. No. 14/747,924
→
APPARATUS AND METHOD FOR VERIFYING THE INTEGRITY OF TRANSFORMED VERTEX DATA IN GRAPHICS PIPELINE PROCESSING
App. No. 14/746,948
→
APPARATUS AND METHOD FOR VERIFYING FRAGMENT PROCESSING RELATED DATA IN GRAPHICS PIPELINE PROCESSING
App. No. 14/747,003
→
RAMP VOLTAGE GENERATOR AND METHOD FOR TESTING AN ANALOG-TO-DIGITAL CONVERTER
App. No. 14/745,641
→
RF CIRCUIT WITH MULTIPLE-DEFINITION RF SUBSTRATE AND CONDUCTIVE MATERIAL VOID UNDER A BIAS LINE
App. No. 14/746,173
→
METHOD FOR TESTING DIFFERENTIAL ANALOG-TO-DIGITAL CONVERTER AND SYSTEM THEREFOR
App. No. 14/745,653
→
ELECTRIC MOTOR THERMAL MANAGEMENT
App. No. 14/745,456
→
SIGNAL ADAPTIVE FILTERING FOR TOUCH DETECTION
App. No. 14/744,310
→
MEMS DEVICE WITH COMMON MODE REJECTION STRUCTURE
App. No. 14/744,693
→
QUAD FLAT NON-LEADED SEMICONDUCTOR PACKAGE WITH WETTABLE FLANK
App. No. 14/743,986
→
VOLTAGE LEVEL SHIFTER FOR HIGH VOLTAGE APPLICATIONS
App. No. 14/743,828
→
TEST CIRCUIT FOR VERY LOW VOLTAGE AND BIAS SCAN TESTING OF INTEGRATED CIRCUIT
App. No. 14/743,977
→
Shared Buffer Management for Variable Length Encoded Data
App. No. 14/743,448
→
DIGITAL DECODING OF BACKSCATTER MODULATED DATA
App. No. 14/743,991
→
INERTIAL SENSOR WITH COUPLE SPRING FOR COMMON MODE REJECTION
App. No. 14/742,452
→
NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM)
App. No. 14/741,674
→
SEMICONDUCTOR DEVICE PACKAGE FOR DEBUGGING AND RELATED FABRICATION METHODS
App. No. 14/741,088
→
PACKAGED SEMICONDUCTOR DEVICES HAVING RIBBON WIRES
App. No. 14/738,937
→
End-to-End Error Detection and Correction
App. No. 14/739,116
→
MULTIPLE PROCESSOR CORE INTERRUPT PRIORITY LEVELS
App. No. 14/739,028
→
VOLTAGE CONTROLLED OSCILLATOR
App. No. 14/651,238
→
CLOCK SOURCE, METHOD FOR DISTRIBUTING A CLOCK SIGNAL AND INTEGRATED CIRCUIT
App. No. 14/651,279
→
SYSTEMS AND METHODS FOR DATA ENCRYPTION
App. No. 14/735,724
→
TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) WITH MAGNETIC TUNNEL JUNCTION (MTJ) DEVICES
App. No. 14/734,742
→
SYSTEMS AND METHODS FOR DRIVING A CONTROL GATE WITH A SELECT GATE SIGNAL IN A SPLIT-GATE NONVOLATILE MEMORY CELL
App. No. 14/734,736
→
A METHOD AND APPARATUS FOR SCAN CHAIN DATA MANAGEMENT
App. No. 14/650,318
→
METHOD AND APPARATUS FOR CALCULATING DELAY TIMING VALUES FOR AN INTEGRATED CIRCUIT DESIGN
App. No. 14/650,319
→
SYSTEMS AND METHODS FOR TESTING A CLAMP FUNCTION FOR INSULATED GATE BIPOLAR TRANSISTORS
App. No. 14/733,589
→
PROTECTED SENSOR FIELD EFFECT TRANSISTORS
App. No. 14/731,795
→
SYSTEM-LEVEL REDUNDANCY IN PCI EXPRESS EQUIPMENT
App. No. 14/728,462
→
PHASE SHIFT AND ATTENUATION CIRCUITS FOR USE WITH MULTIPLE-PATH AMPLIFIERS
App. No. 14/728,196
→
Multiple Connection Management For Bluetooth Low Energy Devices
App. No. 14/728,368
→
METHOD AND APPARATUS FOR ESTIMATING A FRAGMENT COUNT FOR THE DISPLAY OF AT LEAST ONE THREE-DIMENSIONAL OBJECT
App. No. 14/648,713
→
Detector For High Frequency Interrupts
App. No. 14/727,020
→
METHOD AND APPARATUS FOR LIMITING ACCESS TO AN INTEGRATED CIRCUIT (IC)
App. No. 14/727,299
→
BOOT CONTROL SYSTEMS AND METHODS FOR VEHICLES
App. No. 14/725,387
→
SYSTEMS AND METHODS FOR RESOURCE LEAKAGE RECOVERY IN PROCESSOR HARDWARE ENGINES
App. No. 14/726,255
→
SYSTEM FOR RECOVERING UNRESPONSIVE COMMON PUBLIC RADIO INTERFACE (CPRI) NODES
App. No. 14/724,738
→
DATA INTEGRITY CHECK WITHIN A DATA PROCESSING SYSTEM
App. No. 14/722,632
→
METHOD AND APPARATUS FOR ASSEMBLING A SEMICONDUCTOR PACKAGE
App. No. 14/722,810
→
VARIABLE RELUCTANCE SENSOR INTERFACE WITH INTEGRATION BASED ARMING THRESHOLD
App. No. 14/723,420
→
PACKAGE-ON-PACKAGE DEVICE AND CAVITY FORMATION BY SOLDER REMOVAL FOR PACKAGE INTERCONNECTION
App. No. 14/723,007
→
SYSTEM ON CHIP
App. No. 14/647,089
→
CLOCK SIGNAL ALIGNMENT FOR SYSTEM-IN-PACKAGE (SIP) DEVICES
App. No. 14/719,549
→
COMPUTER SYSTEMS AND METHODS FOR EXECUTING CONTEXTS WITH AUTONOMOUS FUNCTIONAL UNITS
App. No. 14/719,390
→
DEVICE WITH A CONDUCTIVE FEATURE FORMED OVER A CAVITY AND METHOD THEREFOR
App. No. 14/719,999
→
PROCESSOR CORE ARRANGEMENT, COMPUTING SYSTEM AND METHODS FOR DESIGNING AND OPERATING A PROCESSOR CORE ARRANGEMENT
App. No. 14/646,988
→
DIGITAL DEVICE
App. No. 14/646,392
→
SOLAR CELL POWERED INTEGRATED CIRCUIT DEVICE AND METHOD THEREFOR
App. No. 14/718,168
→
MECHANISM FOR DATA GENERATION IN DATA PROCESSING SYSTEMS
App. No. 14/718,407
→
METHOD AND APPARATUS FOR CONTROLLING WAKE EVENTS IN A DATA PROCESSING SYSTEM
App. No. 14/718,826
→
DATA PROCESSING DEVICE, METHOD OF EXECUTION ERROR DETECTION AND INTEGRATED CIRCUIT
App. No. 14/646,177
→
METHOD AND SYSTEM TO IMPROVE SOFT-PROGRAMMING TIME IN NON-VOLATILE MEMORY
App. No. 14/717,153
→
SEMICONDUCTOR DEVICES WITH VERTICAL FIELD FLOATING RINGS AND METHODS OF FABRICATION THEREOF
App. No. 14/715,706
→
SYSTEMS AND METHODS FOR SRAM WITH BACKUP NON-VOLATILE MEMORY THAT INCLUDES MTJ RESISTIVE ELEMENTS
App. No. 14/716,729
→
SPORADIC CHANNEL FILTERING
App. No. 14/714,857
→
CIRCUIT GENERATING AN ANALOG SIGNAL USING A PART OF A SIGMA-DELTA ADC
App. No. 14/715,022
→
SYSTEM AND METHOD FOR REGULATING ACCESS TO MEMORY MAPPING INFORMATION AT A MEMORY MANAGEMENT UNIT
App. No. 14/715,196
→
TEST SIGNAL GENERATOR FOR SIGMA-DELTA ADC
App. No. 14/714,946
→
SNR ESTIMATION FOR SOUNDING SIGNALS
App. No. 14/714,818
→
DATA STROBE SIGNAL GENERATION FOR FLASH MEMORY
App. No. 14/715,544
→
SYSTEM FOR ISOLATING INTEGRATED CIRCUIT POWER DOMAINS
App. No. 14/714,333
→
HIGH-SPEED FLYING-CAP LEVEL SHIFTER
App. No. 14/714,341
→
VOLTAGE REGULATOR WITH EXTENDED MINIMUM TO MAXIMUM LOAD CURRENT RATIO
App. No. 14/714,256
→
MULTIPLE MODE POWER REGULATOR
App. No. 14/713,116
→
PHASE CORRECTION IN A DOHERTY POWER AMPLIFIER
App. No. 14/714,036
→
Method of Offloading Cyclic Redundancy Check on Portions of a Packet
App. No. 14/713,632
→