INTEGRATED CIRCUIT INCLUDING OVERLAPPING SCAN DOMAINS
An integrated circuit includes overlapping scan domains, wherein at least one scan domain of the integrated circuit includes some, but not all, of the synchronous logic elements, logic gates, and signal paths of a different scan domain. Each scan domain includes a scan wrapper to receive test patterns generated to test the logic mix for that domain. The test patterns are propagated through the logic mix of the scan domain to generate corresponding output patterns, which are compared to expected results for that scan domain. By overlapping the scan domains, test coverage of the integrated circuit can be increased without substantially increasing testing time. The test patterns applied to the integrated circuit can be pruned to remove duplicate patterns generated for overlapping scan domains.
1 . An integrated circuit comprising:
a first scan domain comprising a first plurality of logic elements and a first scan wrapper to apply a first set of test patterns to the first plurality of logic elements; and
a second scan domain comprising a second plurality of logic elements and a second scan wrapper to apply a second set of test patterns to the second plurality of logic elements, the second scan domain overlapping with the first scan domain.
2 . The integrated circuit of claim 1 wherein the first scan domain includes input/output signal lines between a first functional module of the integrated circuit and a second functional module of the integrated circuit, and wherein the second scan domain does not include the input/output signal lines.
3 . The integrated circuit of claim 2 , wherein the second scan domain includes the first functional module of the integrated circuit and does not include the second functional module.
4 . The integrated circuit of claim 1 , further comprising:
a third scan domain comprising a third plurality of logic elements and a third scan wrapper to apply a third set of test patterns to the third plurality of logic elements, the third scan domain overlapping with the first scan domain.
5 . The integrated circuit of claim 4 , wherein the third scan domain overlaps with the second scan domain.
6 . The integrated circuit of claim 5 , wherein the third scan domain does not overlap with the second scan domain.
7 . The integrated circuit of claim 1 , wherein:
the first scan domain comprises the logic elements of a first functional module of the integrated circuit and a minimum number of logic elements of a second functional module of the integrated circuit to provide test coverage of signal paths between the first functional module and the second functional module.
8 . The integrated circuit of claim 1 , wherein the integrated circuit is incorporated in a consumer device.
9 . An integrated circuit, comprising:
a first scan domain including a portion of a first functional module, a portion of a second functional module, and input/output signal lines between the first functional module and the second functional module; and
a second scan domain that overlaps with the first scan domain, the second scan domain including the portion of the first functional module and excluding the portion of the second functional module.
10 . The integrated circuit of claim 9 , wherein the second scan domain does not include the input/output signal lines between the first functional module and the second functional module.
11 . The integrated circuit of claim 9 , wherein the first scan domain includes a first scan wrapper to apply a first set of test patterns to the first scan domain.
12 . The integrated circuit of claim 11 , wherein the second scan domain includes a second scan wrapper to apply a second set of test patterns to the second scan domain, the second set of test patterns based on the first set of test patterns.
13 . A method, comprising:
applying a first set of test patterns to a first scan domain of an integrated circuit, the first scan domain comprising a first plurality of logic elements; and
applying a second set of test patterns to a second scan domain of the integrated circuit, the second scan domain comprising a second plurality of logic elements, the second scan domain overlapping with the first scan domain.
14 . The method of claim 13 , further comprising:
generating the second set of test patterns based on the first set of test patterns.
15 . The method of claim 14 , wherein generating the second set of test patterns comprises:
generating a third set of test patterns; and
generating the second set of test patterns by removing from the third set of test patterns those test patterns that match test patterns of the first set of test patterns.
16 . The method of claim 13 , wherein the first scan domain includes logic elements not included in the second scan domain and the second scan domain includes logic elements not included in the first scan domain.
17 . The method of claim 13 wherein the first scan domain includes input/output signal lines between a first functional module of the integrated circuit and a second functional module of the integrated circuit, and wherein the second scan domain does not include the input/output signal lines.
18 . The method of claim 17 , wherein the second scan domain includes the first functional module of the integrated circuit and does not include the second functional module.
19 . The method of claim 13 , further comprising:
applying a third set of test patterns to a third scan domain comprising a third plurality of logic elements, the third scan domain overlapping with the first scan domain.
20 . The method of claim 19 , wherein the third scan domain overlaps with the second scan domain.