Patent Application

App. No. 14/646,392

Abstract

Claims (27)

1 . A digital device comprising:

one or more requestor units;

one or more responder units;

a bus, each of said responder units being connected to said one or more requestor units via said bus, wherein each of said one or more responder units comprises a plurality of responder elements which are accessible by said requestor units via said bus and which include one or more critical responder elements; and

one or more wrapper units, wherein each of said wrapper units connects one of said responder units to said bus and comprises:

an interface unit arranged to enable said requestor units to access the responder elements of the respective responder unit associated with the respective wrapper unit; and

a checksum unit arranged to respond to any write access to any one of said critical responder elements by computing and storing a reference checksum; wherein said checksum unit is arranged to compute said reference checksum by applying a checksum algorithm to a subset of said critical responder elements, said subset comprising at least said write-accessed critical responder element.

2 . The digital device of claim 1 , wherein each of said wrapper units further comprises a configuration unit which is configurable to define any one of said responder elements as a critical responder element

3 . The digital device of claim 2 , wherein said configuration unit is hardwired at synthesis time or one-time configurable at device startup.

4 . The digital device of claim 1 , wherein said subset comprises only said write-accessed responder element.

5 . The digital device of claim 1 , wherein said subset comprises any combination of critical responder elements among said critical responder elements.

6 . The digital device of claim 1 , further comprising a shared unit connected to each of said one or more wrapper units and arranged to provide one or more functions which are common to said one or more wrapper units.

7 . The digital device of claim 1 , wherein said one or more commons functions include generating said reference checksum.

8 . The digital device of claim 1 , wherein each of said wrapper units further comprises a verification unit arranged to perform an integrity test, wherein the verification unit is configured to:

operate the interface unit for reading the data content of a group of critical memory elements including at least one of the critical responder elements,

compute a verification checksum by re-applying said checksum algorithm to the data content of said group of critical memory elements,

verify whether said verification checksum is identical to said reference checksum, and

trigger an error action if said verification checksum is not identical to the respective reference checksum.

9 . The digital device of claim 8 , wherein said reading of said data content is not visible to any other block than the involved wrapper unit and the corresponding responder unit.

10 . The digital device of claim 8 , arranged to be clocked by a first clock signal and comprising a clock divider for generating a second clock signal having a lower clock rate than said first clock signal, wherein said verification unit arranged to repeat said integrity test at a triggering edge of said second clock signal.

11 . The digital device of claim 8 , arranged to repeat said integrity test in parallel or in series

for any subset of the wrapper units and

for any subset of the critical memory elements of a wrapper units 14 within the said subset of wrapper units.

12 . The digital device of claim 8 , wherein said verification unit is arranged to perform said integrity test while none of said requestor units is accessing the respective responder unit.

13 . The digital device of claim 1 , wherein said checksum is or comprises an error detection and correction code.

14 . The digital device of claim 1 , wherein said digital device is a system on chip.

15 . The digital device of claim 1 , wherein said responder elements are registers.

Assignments (24)